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Merge pull request #6535 from rocknitive/fix-stm32-buffered-uart-write
stm32/uart: fix embedded_io::Write impl for BufferedUartTx
2 parents 696b630 + 5762410 commit fa8bacd

1 file changed

Lines changed: 36 additions & 29 deletions

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embassy-stm32/src/usart/buffered.rs

Lines changed: 36 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -728,38 +728,31 @@ impl<'d> BufferedUartRx<'d> {
728728
impl<'d> BufferedUartTx<'d> {
729729
async fn write(&self, buf: &[u8]) -> Result<usize, Error> {
730730
poll_fn(move |cx| {
731+
if buf.is_empty() {
732+
return Poll::Ready(Ok(0));
733+
}
734+
731735
let state = self.state;
732736
state.tx_done.store(false, Ordering::Release);
733737

734738
let empty = state.tx_buf.is_empty();
735739

736-
if state.tx_buf.len() < buf.len() {
737-
return Poll::Ready(Err(Error::BufferTooLong));
738-
}
739-
740-
if state.tx_buf.len() - state.tx_buf.available() < buf.len() {
740+
let mut tx_writer = unsafe { state.tx_buf.writer() };
741+
let data = tx_writer.push_slice();
742+
if data.is_empty() {
743+
state.tx_waker.register(cx.waker());
741744
return Poll::Pending;
742745
}
743746

744-
let mut written: usize = 0;
745-
let mut tx_writer = unsafe { state.tx_buf.writer() };
746-
while written != buf.len() {
747-
let data = tx_writer.push_slice();
748-
if data.is_empty() {
749-
state.tx_waker.register(cx.waker());
750-
return Poll::Pending;
751-
}
752-
let n = data.len().min(buf.len() - written);
753-
data[..n].copy_from_slice(&buf[written..written + n]);
754-
written = written + n;
755-
tx_writer.push_done(n);
756-
}
747+
let n = data.len().min(buf.len());
748+
data[..n].copy_from_slice(&buf[..n]);
749+
tx_writer.push_done(n);
757750

758751
if empty {
759752
self.info.interrupt.pend();
760753
}
761754

762-
Poll::Ready(Ok(written))
755+
Poll::Ready(Ok(n))
763756
})
764757
.await
765758
}
@@ -779,29 +772,31 @@ impl<'d> BufferedUartTx<'d> {
779772
}
780773

781774
fn blocking_write(&self, buf: &[u8]) -> Result<usize, Error> {
775+
if buf.is_empty() {
776+
return Ok(0);
777+
}
778+
782779
loop {
783780
let state = self.state;
784781
state.tx_done.store(false, Ordering::Release);
785782

786783
let empty = state.tx_buf.is_empty();
787784

788-
let mut written: usize = 0;
789785
let mut tx_writer = unsafe { state.tx_buf.writer() };
790-
while written != buf.len() {
791-
let data = tx_writer.push_slice();
792-
if !data.is_empty() {
793-
let n = data.len().min(buf.len() - written);
794-
data[..n].copy_from_slice(&buf[written..written + n]);
795-
written = written + n;
796-
tx_writer.push_done(n);
797-
}
786+
let data = tx_writer.push_slice();
787+
if data.is_empty() {
788+
continue;
798789
}
799790

791+
let n = data.len().min(buf.len());
792+
data[..n].copy_from_slice(&buf[..n]);
793+
tx_writer.push_done(n);
794+
800795
if empty {
801796
self.info.interrupt.pend();
802797
}
803798

804-
return Ok(written);
799+
return Ok(n);
805800
}
806801
}
807802

@@ -995,6 +990,18 @@ impl<'d> embedded_io::Write for BufferedUartTx<'d> {
995990
}
996991
}
997992

993+
impl<'d> embedded_io::WriteReady for BufferedUart<'d> {
994+
fn write_ready(&mut self) -> Result<bool, Self::Error> {
995+
embedded_io::WriteReady::write_ready(&mut self.tx)
996+
}
997+
}
998+
999+
impl<'d> embedded_io::WriteReady for BufferedUartTx<'d> {
1000+
fn write_ready(&mut self) -> Result<bool, Self::Error> {
1001+
Ok(!self.state.tx_buf.is_full())
1002+
}
1003+
}
1004+
9981005
impl<'d> embedded_hal_02::serial::Read<u8> for BufferedUartRx<'d> {
9991006
type Error = Error;
10001007

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