From ba351c48fadaf32514f50f7af46038efbe83ad81 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sun, 19 Oct 2025 16:52:37 -0700
Subject: [PATCH] SystemVerilog: KNOWNBUG test for cover disable iff

---
 regression/verilog/SVA/cover_sequence5.desc |  9 +++++++++
 regression/verilog/SVA/cover_sequence5.sv   | 15 +++++++++++++++
 2 files changed, 24 insertions(+)
 create mode 100644 regression/verilog/SVA/cover_sequence5.desc
 create mode 100644 regression/verilog/SVA/cover_sequence5.sv

diff --git a/regression/verilog/SVA/cover_sequence5.desc b/regression/verilog/SVA/cover_sequence5.desc
new file mode 100644
index 000000000..0789e72bf
--- /dev/null
+++ b/regression/verilog/SVA/cover_sequence5.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+cover_sequence5.sv
+--bound 10
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This gives the wrong answer.
diff --git a/regression/verilog/SVA/cover_sequence5.sv b/regression/verilog/SVA/cover_sequence5.sv
new file mode 100644
index 000000000..38c09492e
--- /dev/null
+++ b/regression/verilog/SVA/cover_sequence5.sv
@@ -0,0 +1,15 @@
+module main(input clk);
+
+  // count up
+  int x = 0;
+
+  always_ff @(posedge clk)
+    x++;
+
+  // never passes, owing to disable iff
+  p0: cover sequence (disable iff (1) 1);
+
+  // passes when reaching x=10
+  p1: cover sequence (disable iff (x<10) 1);
+
+endmodule