Verilog: tests for arithmetic on x/z

regression/verilog/expressions/div1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+div1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The result is wrong.

regression/verilog/expressions/div1.sv

@@ -0,0 +1,13 @@
+module main;
+
+  // Any arithmetic with x or z returns x.
+  initial assert(32'bx / 1 === 32'hxxxx_xxxx);
+  initial assert(32'bz / 1 === 32'hxxxx_xxxx);
+  initial assert(1 / 32'bx === 32'hxxxx_xxxx);
+  initial assert(1 / 32'bz === 32'hxxxx_xxxx);
+
+  // Division by zero returns x
+  initial assert(1 / 0 === 32'hxxxx_xxxx);
+  initial assert(1 / 0 === 32'hxxxx_xxxx);
+
+endmodule

regression/verilog/expressions/minus1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+minus1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The result is wrong.

regression/verilog/expressions/minus1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // Any arithmetic with x or z returns x.
+  initial assert(32'bx - 1 === 32'hxxxx_xxxx);
+  initial assert(32'bz - 1 === 32'hxxxx_xxxx);
+  initial assert(1 - 32'bx === 32'hxxxx_xxxx);
+  initial assert(1 - 32'bz === 32'hxxxx_xxxx);
+
+endmodule

regression/verilog/expressions/mod1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+mod1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The result is wrong.

regression/verilog/expressions/mod1.sv

@@ -0,0 +1,13 @@
+module main;
+
+  // Any arithmetic with x or z returns x.
+  initial assert(32'bx % 1 === 32'hxxxx_xxxx);
+  initial assert(32'bz % 1 === 32'hxxxx_xxxx);
+  initial assert(1 % 32'bx === 32'hxxxx_xxxx);
+  initial assert(1 % 32'bz === 32'hxxxx_xxxx);
+
+  // mod-by-zero returns x
+  initial assert(1 % 0 === 32'hxxxx_xxxx);
+  initial assert(1 % 0 === 32'hxxxx_xxxx);
+
+endmodule

regression/verilog/expressions/mult1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+mult1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The result is wrong.

regression/verilog/expressions/mult1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // Any arithmetic with x or z returns x.
+  initial assert(32'bx * 0 === 32'hxxxx_xxxx);
+  initial assert(32'bz * 0 === 32'hxxxx_xxxx);
+  initial assert(0 * 32'bx === 32'hxxxx_xxxx);
+  initial assert(0 * 32'bz === 32'hxxxx_xxxx);
+
+endmodule

regression/verilog/expressions/plus1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+plus1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The result is wrong.

regression/verilog/expressions/plus1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // Any arithmetic with x or z returns x.
+  initial assert(32'bx + 1 === 32'hxxxx_xxxx);
+  initial assert(32'bz + 1 === 32'hxxxx_xxxx);
+  initial assert(1 + 32'bx === 32'hxxxx_xxxx);
+  initial assert(1 + 32'bz === 32'hxxxx_xxxx);
+
+endmodule

regression/verilog/expressions/power3.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+power3.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The result is wrong.

regression/verilog/expressions/power3.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // Any arithmetic with x or z returns x.
+  initial assert('bx ** 1 === 'x);
+  initial assert('bz ** 1 === 'x);
+  initial assert(1 ** 'bx === 'x);
+  initial assert(1 ** 'bz === 'x);
+
+endmodule

regression/verilog/expressions/unary_minus1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+unary_minus1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The result is wrong.

regression/verilog/expressions/unary_minus1.sv

@@ -0,0 +1,6 @@
+module main;
+
+  // Any arithmetic with x or z returns x.
+  initial assert(-32'bz === 32'hxxxx_xxxx);
+
+endmodule

regression/verilog/expressions/unary_plus1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+unary_plus1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The result is wrong.

regression/verilog/expressions/unary_plus1.sv

@@ -0,0 +1,14 @@
+module main;
+
+  // Any arithmetic with x or z normally returns x.
+  // IVerilog, VCS, Questa, Riviera say that +'bz is z.
+  // XCelium says it's 'x.
+
+  // 1800-2017 11.4.3 says "For the arithmetic operators, if any operand bit
+  // value is the unknown value x or the high-impedance value z, then the
+  // entire result value shall be x."
+  // But it also says "Unary plus m (same as m)" in Table 11-5.
+
+  initial assert(+32'bz === 32'hxxxx_xxxx);
+
+endmodule