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ppc: Add mfcr and mtcrf support to assembler
1 parent 880d2b3 commit c201c65

2 files changed

Lines changed: 18 additions & 0 deletions

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src/Cemu/PPCAssembler/ppcAssembler.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -307,6 +307,8 @@ const char* ppcAssembler_getInstructionName(uint32 ppcAsmOp)
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case PPCASM_OP_MTLR: return "MTLR";
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case PPCASM_OP_MFCTR: return "MFCTR";
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case PPCASM_OP_MTCTR: return "MTCTR";
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case PPCASM_OP_MFCR: return "MFCR";
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case PPCASM_OP_MTCRF: return "MTCRF";
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case PPCASM_OP_CROR: return "CROR";
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case PPCASM_OP_CRNOR: return "CRNOR";
@@ -1192,6 +1194,8 @@ PPCInstructionDef ppcInstructionTable[] =
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{PPCASM_OP_MTLR, 0, 31, 467, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, 0, 0, nullptr, {EncodedOperand_GPR(21)}, {EncodedConstraint_FixedSPR(8)} },
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{PPCASM_OP_MFCTR, 0, 31, 339, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, 0, 0, nullptr, {EncodedOperand_GPR(21)}, {EncodedConstraint_FixedSPR(9)} },
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{PPCASM_OP_MTCTR, 0, 31, 467, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, 0, 0, nullptr, {EncodedOperand_GPR(21)}, {EncodedConstraint_FixedSPR(9)} },
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{PPCASM_OP_MFCR, 0, 31, 19, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, 0, 0, nullptr, {EncodedOperand_GPR(21)}},
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{PPCASM_OP_MTCRF, 0, 31, 144, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, 0, 0, nullptr, {EncodedOperand_IMM(12, 8, false), EncodedOperand_GPR(21)}},
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{PPCASM_OP_ADD, 0, 31, 266, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, C_MASK_RC, 0, nullptr, {EncodedOperand_GPR(21), EncodedOperand_GPR(16), EncodedOperand_GPR(11)} },
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{PPCASM_OP_ADD_, 0, 31, 266, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, C_MASK_RC, C_BIT_RC, nullptr, {EncodedOperand_GPR(21), EncodedOperand_GPR(16), EncodedOperand_GPR(11)} },
@@ -3591,6 +3595,18 @@ void ppcAsmTestDisassembler()
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_testAsm(0x6fe9ff00, "xoris r9, r31, 0xFF00");
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_testAsm(0x6fe9ffff, "xoris r9, r31, 0xFFFF");
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// mfcr / mtcrf
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_testAsm(0x7D800026, "mfcr r12");
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disassemble(0x7D800026, PPCASM_OP_MFCR);
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checkOperandMask(true);
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checkOpGPR(0, 12);
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_testAsm(0x7D808120, "mtcrf 8, r12");
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disassemble(0x7D808120, PPCASM_OP_MTCRF);
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checkOperandMask(true, true);
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checkOpImm(0, 8);
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checkOpGPR(1, 12);
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// data directives
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_testAsmArray({ 0x00, 0x00, 0x00, 0x01 }, ".int 1");
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_testAsmArray({ 0x00, 0x00, 0x00, 0x01, 0x11, 0x22, 0x33, 0x44 }, ".int 1, 0x11223344");

src/Cemu/PPCAssembler/ppcAssembler.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -278,6 +278,8 @@ enum PPCASM_OP
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// cache & misc
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PPCASM_OP_ISYNC,
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PPCASM_OP_MFCR, // move from condition register
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PPCASM_OP_MTCRF, // move to condition register fields
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// extended mnemonics
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PPCASM_OP_NOP, // ORI

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