Is it possible to configure SPRAM using Amaranth?

[joshkahn42]

Hi,
I am writing code using Amaranth for a Lattice iCE40 UltraPLus UP5k.
Is it possible to create a memory array in Amaranth that will use the FPGA's SPRAM instead of the RAM?
I am currently using a memory array: https://amaranth-lang.org/docs/amaranth/latest/stdlib/memory.html

I am synthesizing the output verilog code with yosys and need to move some of the resources from RAM to SPRAM.

[whitequark]

SPRAM inference is highly dependent on the toolchain and the exact instantiation of the memory. Please attach an example of source code that you're using to create a memory, minimized to only contain the memory-related parts.

[joshkahn42]

Yes, I know how to call out SPRAM directly from verilog, but I would like to have all the code in Amaranth if possible without modifying verilog files directly afterwards. The module I am working on implementing is just an easy way to access (read and write) a double buffered 2 dimensional array (3 dimensions spread out in memory as a single dimensional array and then indexed with multiplication and addition like C pointers).
Code is below:

from typing import List, Tuple
import math
from amaranth import *
from amaranth.build import Platform
from amaranth.lib.memory import Memory
from util import main
import matplotlib.pyplot as plt
import numpy as np
import os
from amaranth.lib import data, enum

NUM_BINS = 8
NUM_REREF_CHANNELS = 60 

class DataBuffer(Elaboratable):
    """
    Read/Write memory double buffered
    Each of the two arrays contains data of an unfolded 2D array of size [num_channels][num_bins]

    +------------------+-------------+-------------+-------------+----------------------+
    |     \\ channel-> | 0           | 1           | ...         | num_reref_channels-1 |
    |  bin \\          |             |             |             |                      |
    +------------------+-------------+-------------+-------------+----------------------+
    |                0 | val1 | val2 | val1 | val2 | val1 | val2 | val1 | val2          |
    +------------------+-------------+-------------+-------------+----------------------+
    |                1 | val1 | val2 | val1 | val2 | val1 | val2 | val1 | val2          |
    +------------------+-------------+-------------+-------------+----------------------+
    |              ... | val1 | val2 | val1 | val2 | val1 | val2 | val1 | val2          |
    +------------------+-------------+-------------+-------------+----------------------+
    |       num_bins-1 | val1 | val2 | val1 | val2 | val1 | val2 | val1 | val2          |
    +------------------+-------------+-------------+-------------+----------------------+

    Unfolded array is each row followed by the next. row0,row1,etc. Similar to C indexing of 2D arrays
    """

    def __init__(self, data_size):
        """Initialization. Specifies inputs and outputs. 
        Note that Amaranth generates clk and rst signals automatically when converting to verilog
        """
        #Parameters (constants chosen on compilation)
        self.param_data_size = data_size #size of input data

        #Inputs
        self.in_val1 = Signal(signed(self.param_data_size)) #input for single entry in table
        self.in_val2 = Signal.like(self.in_val1) #input for single entry in table
        self.in_write_buff = Signal(1) #Buffer input for reading
        self.in_write_bin = Signal(range(NUM_BINS)) #Bin input
        self.in_write_channel = Signal(range(NUM_REREF_CHANNELS)) #Channel input
        self.in_write_en = Signal(1)  #Enable input for writing to memory

        self.in_read_buff = Signal(1) #Buffer input for reading
        self.in_read_bin = Signal(range(NUM_BINS)) #Bin input for reading
        self.in_read_channel = Signal(range(NUM_REREF_CHANNELS)) #Channel input for reading

        #Outputs
        self.out_val1 = Signal.like(self.in_val1) 
        self.out_val2 = Signal.like(self.in_val1) 

    #Define input ports to return as text 
    def in_ports(self):
        return [self.in_val1, self.in_val2, self.in_write_buff, self.in_write_bin, self.in_write_channel, self.in_write_en, self.in_read_buff, self.in_read_channel, self.in_read_bin]
    
    #Define output ports to return as text 
    def out_ports(self):
        return [self.out_val1, self.out_val2]

    def elaborate(self, _: Platform) -> Module: 
        """Implements the logic for the module."""
        m = Module()

        # Create memory to store values. Double buffered.
        # Organized so have NUM_BINS rows, each with NUM_REREF_CHANNELS worth of data.
        # This structure is then double buffered
        # Final structure is essentially a 3D array of size [2][NUM_BINS][NUM_REREF_CHANNELS]

        memory = Memory(shape = 2*self.param_data_size, depth = 2 * NUM_REREF_CHANNELS * NUM_BINS, init = [0])
        m.submodules.memory = memory
        wr_port = memory.write_port()
        m.d.comb += wr_port.en.eq(self.in_write_en)
        with m.If(self.in_write_en):
            m.d.comb += wr_port.addr.eq(self.in_write_channel + (self.in_write_bin * NUM_REREF_CHANNELS) + (self.in_write_buff * NUM_BINS * NUM_REREF_CHANNELS)) #Unfolded array indexing
            m.d.comb += wr_port.data.eq(Cat(self.in_val1, self.in_val2))

        rd_port = memory.read_port(transparent_for = (wr_port, )) #Make read transparent to write so can read and write in same clock cycle
        m.d.comb += rd_port.addr.eq(self.in_read_channel + (self.in_read_bin * NUM_REREF_CHANNELS) + (self.in_read_buff * NUM_BINS * NUM_REREF_CHANNELS)) #Unfolded array indexing
        m.d.comb += self.out_val1.eq(rd_port.data[:self.param_data_size])
        m.d.comb += self.out_val2.eq(rd_port.data[self.param_data_size:])  

        return m

[whitequark]

Ah, I see the problem. Right now we don't support uninitialized memories in Amaranth due to the non-determinism inherent in these; this is tracked in #824. In order to work around this, you could extend the Yosys script used in your build to forcibly remove the initial value from the memory; the Yosys setattr -unset init ... command could be used for that. Let me know if you need further assistance.

[joshkahn42]

Interesting thread there, thanks for the link.
Is that something I would do in the verilog generation from within Amaranth? Or once I have the verilog output and synthesize that with yosys?

[whitequark]

Amaranth doesn't allow extending Verilog generation within back.verilog, so if you aren't using amaranth.build or the board files, you will have to do this on your own when you call Yosys. If you are using amaranth.build or the board files, you can extend the existing Yosys script.