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Add nitefuryii/litefury
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‎amaranth_boards/nitefury.py‎

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import os
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import subprocess
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import textwrap
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import unittest
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from amaranth.build import *
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from amaranth.vendor import XilinxPlatform
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from .resources import *
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__all__ = ["NitefuryIIPlatform", "LitefuryPlatform"]
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class _BasePlatform(XilinxPlatform):
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speed = "2"
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default_clk = "clk200"
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resources = [
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Resource("clk200", 0, DiffPairs(p="J19", n="H19", dir="i"),
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Clock(200e6), Attrs(IOSTANDARD="DIFF_SSTL15")),
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# 4 Programmable LEDs
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*LEDResources(pins="G3 H3 G4 H4", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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# SPIFlash
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*SPIFlashResources(0,
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cs_n="T19", clk="L16", copi="P22", cipo="R22", wp_n="P21", hold_n="R21",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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# 1 M.2 indicator LED
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Resource("m2led", 0, Pins("M1"), Attrs(IOSTANDARD="LVCMOS33")),
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# PCIE
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Resource("pcie", 0,
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Subsignal("clkreq", PinsN("G1", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
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Subsignal("rst", PinsN("J1", dir="o"), Attrs(IOSTANDARD="LVCMOS33", PULLUP=1)),
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Subsignal("clk", DiffPairs(p="F6", n="E6", dir="i"), Attrs(IOSTANDARD="DIFF_SSTL15")),
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Subsignal("rx", DiffPairs(p="B10 B8 D11 D9", n="A10 A8 C11 C9", dir="i")),
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Subsignal("tx", DiffPairs(p="B6 B4 D5 D7", n="A6 A4 C5 C7", dir="o")),
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),
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# DDR
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Resource("ddr3", 0,
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Subsignal("rst", PinsN("K16", dir="o"), Attrs(IOStandard="LVCMOS15")),
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Subsignal("clk", DiffPairs(p="K17", n="J17", dir="o")),
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Subsignal("clk_en", Pins("H22", dir="o")),
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# Subsignal("cs", PinsN("U8", dir="o")),
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Subsignal("we", PinsN("L16", dir="o")),
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Subsignal("ras", PinsN("H20", dir="o")),
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Subsignal("cas", PinsN("K18", dir="o")),
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Subsignal("a", Pins("M15 L21 M16 L18 K21 M18 M21 N20 M20 N19 J21 M22 K22 N18 N22 J22", dir="o")),
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Subsignal("ba", Pins("L19 J20 L20", dir="o")),
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Subsignal("dqs", DiffPairs(p="F18 B21", n="E18 A21", dir="io"),
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Attrs(IOSTANDARD="DIFF_SSTL135")),
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Subsignal("dq", Pins("D19 B20 E19 A20 F19 C19 F20 C18 E22 G21 D20 E21 C22 D21 B22 D22", dir="io"),
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Attrs(IN_TERM="UNTUNED_SPLIT_50")),
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Subsignal("dm", Pins("A19 G22", dir="o")),
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Subsignal("odt", Pins("K19", dir="o")),
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Attrs(IOSTANDARD="SSTL15", SLEW="FAST"),
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),
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]
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connectors = []
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def toolchain_prepare(self, fragment, name, **kwargs):
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overrides = {
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"script_before_bitstream":
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"""
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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""",
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"script_after_bitstream":
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"write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {name}.bit\" -file {name}.bin".format(name=name),
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"add_constraints":
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"""
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set_property INTERNAL_VREF 0.675 [get_iobanks 34]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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"""
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}
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return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
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def toolchain_program(self, product, name, *, programmer="openfpgaloader", flash=True):
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assert programmer in ("vivado", "openfpgaloader")
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if programmer == "vivado":
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if flash:
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# It does not appear possible to reset the FPGA via TCL after
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# flash programming.
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with product.extract("{}.bin".format(name)) as bitstream_filename:
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cmd = textwrap.dedent("""
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open_hw_manager
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connect_hw_server
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open_hw_target
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current_hw_device [lindex [get_hw_devices xc7a*] 0]]
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create_hw_cfgmem -hw_device [current_hw_device] s25fl256sxxxxxx0-spi-x1_x2_x4
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set_property PROGRAM.FILES {{{}}} [current_hw_cfgmem]
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set_property PROGRAM.ADDRESS_RANGE {{use_file}} [current_hw_cfgmem]
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set_property PROGRAM.BLANK_CHECK 1 [current_hw_cfgmem]
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set_property PROGRAM.ERASE 1 [current_hw_cfgmem]
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set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]
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set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]
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create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]
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program_hw_devices
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program_hw_cfgmem
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close_hw_manager
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puts "Vivado TCL cannot reset boards. Reset or power-cycle your board now."
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""").format(bitstream_filename).encode("utf-8")
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subprocess.run(["vivado", "-nolog", "-nojournal", "-mode", "tcl"], input=cmd, check=True)
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else:
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with product.extract("{}.bit".format(name)) as bitstream_filename:
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cmd = textwrap.dedent("""
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open_hw_manager
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connect_hw_server
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open_hw_target
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current_hw_device [lindex [get_hw_devices] 0]
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set_property PROGRAM.FILE {{{}}} [current_hw_device]
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program_hw_devices
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close_hw_manager
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""").format(bitstream_filename).encode("utf-8")
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subprocess.run(["vivado", "-nolog", "-nojournal", "-mode", "tcl"], input=cmd, check=True)
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else:
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# openfpgaloader
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openfpgaloader = os.environ.get("OPENFPGALOADER", "openFPGALoader")
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with product.extract("{}.bin".format(name)) as fn:
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# TODO: @timkpaine has digilent_hs3 cable
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subprocess.check_call([openfpgaloader, "-c", "digilent_hs3", fn])
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class LitefuryPlatform(_BasePlatform):
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device = "xc7a100t"
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package = "fgg484"
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class NitefuryIIPlatform(_BasePlatform):
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device = "xc7a200t"
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package = "fbg484"
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class TestCase(unittest.TestCase):
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def test_smoke(self):
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from .test.blinky import Blinky
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NitefuryIIPlatform().build(Blinky(), do_build=False)
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if __name__ == "__main__":
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from .test.blinky import *
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NitefuryIIPlatform().build(Blinky(), do_program=True)

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