Does SDAccel support DDR pages?

[shmsong]

Hi I am currently developing a AI application on AWS. The DRAM onboard seems to be 64GB. So if I want to use the whole DDR bank while not mapping all the data in the host application memory space. would this be possible?

Say my host process only has 2GB of memory allocated from linux but I am carrying 16GB data around with the help of the file system but I still want a copy of the 16GB around for the kernel.

[uday610]

@buaobuao, if I understood correctly this is not supported. Do you mean you would like to transfer the whole 16GB data to the kernel (via DDR) and then kernel will start working? Then I don't think we can do this today. Why you cannot break your data into smaller segments and transfer them in a pipelined fashion overlapping with kernel execution? You need to enqueue kernel multiple times and each time it will work on each segment?

Thanks
Uday

[shmsong]

Hi Uday610, Thanks for your answer. I agree that using 16GB in one shot wouldn't work, and I probably needed more of your help. I was thinking about using the memory mapping some how. Say if I want to save 10GB on the global memory, with DDR. Would the C++ kernel have access to the whole 16GB space and use the kernel to move the data to the gmem 1GB by 1GB?

[uday610]

Hello @buaobuao , I am not sure what you mean by "saving 10GB on the global memory". Yes, the kernel can access the whole 16GB that's not a problem. But what I wrote above is something different. I wrote about enqueuing the kernel multiple times with each time working on a small amount of data, let's say 1GB.

By the way, I don't think the further help related to your design will be applicable in this thread. These threads are for raising/discussing the SDAccel Tutorial examples used in this repo. If you need support/suggestion/advice for your design, then I think you can ask in the following places:

1. AWS FPGA Development Forum (https://forums.aws.amazon.com/forum.jspa?forumID=243&start=0)

2. Xilinx SDAccel Forum: https://forums.xilinx.com/t5/SDAccel/bd-p/SDx

3. Or you can email me to my Xilinx ID (you can find my email address in my GitHub profile).

Thanks
Uday