NPU cocotb suite: execute the vplan, lock-step vs golden model, close coverage

[WJiangH]

Deliverable via PR with manifest: hw/dv/npu/Makefile + test_npu.py (+ BUGS.md if failures).

Inputs: hw/dv/npu/vplan.md (your test contract — implement every sim-tagged row), hw/dv/common/models/npu.py (golden model; PYTHONPATH wired by flow/sim.mk), docs/spec/npu.md + soc_1.md for interface contracts. Clean room: never read hw/rtl/npu/ sources — reference the file path in VERILOG_SOURCES only; expected values come from the golden model exclusively.

Requirements:

• Makefile: include ../../../flow/sim.mk, TOPLEVEL=npu (confirm the module name from the spec's interface section, not by reading RTL), VERILOG_SOURCES=$(REPO_ROOT)/hw/rtl/npu/*.sv paths.
• Directed test per sim-tagged vplan row: CSR/descriptor programming, weight-FIFO ingress incl. stall/backpressure, quantization edge vectors from the golden model's self-check set, GEMV end-to-end vs golden lock-step, irq timing (compute-done vs stream-done ordering), error descriptor handling.
• Seeded constrained-random stream test (log seed; must replay with SEED=).
• Run make sim MOD=npu until conclusive. A FAILING test that traces to RTL-vs-spec divergence is a DELIVERABLE: file it in hw/dv/npu/BUGS.md (repro command + spec NPU-NN cite + expected vs observed) and keep going — do NOT touch RTL. If the golden model itself contradicts the spec, file that distinctly (spec-side issue).
• COVERAGE=1 run; report line/toggle numbers vs the 90% gate.
  All context in-repo. Paste real tool output in the manifest — counts will be audited.

[claude]

Claiming this issue — dv-engineer. Will implement hw/dv/npu/{Makefile,test_npu.py} per vplan.md, run make sim MOD=npu (+COVERAGE=1), and file hw/dv/npu/BUGS.md for any RTL-vs-spec divergence. Clean room: will not read hw/rtl/npu/ sources.