Enable the full RV64G in the hardware targets.

Technically, this gives GCC license to emit floating-point instructions.
We're fine with this for now, because we currently _do_ context-switch
floating-point registers in the kernel.

This un-breaks the build on those platforms -- it was previously broken
because the assembler would refuse to emit a floating-point load/store
that wasn't permitted by the -march value.

Signed-off-by: Amy Ringo <me@remexre.com>

Author: remexre

src/targets/riscv64/milkv-duos.mak

@@ -2,5 +2,5 @@
 #
 # SPDX-License-Identifier: GPL-3.0-or-later
 
-kernel-cflags += -march=rv64imac_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_zicsr_zicntr_zihpm -mtune=thead-c906
+kernel-cflags += -march=rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_zicsr_zicntr_zihpm -mtune=thead-c906
 target-qemuflags = --machine virt --cpu thead-c906 --smp 1 -m 512M

src/targets/riscv64/milkv-jupiter.mak

@@ -2,5 +2,5 @@
 #
 # SPDX-License-Identifier: GPL-3.0-or-later
 
-kernel-cflags += -march=rv64imac_zicsr_zicntr_zihpm_zba_zbb_zbs_zihintpause_zicbom_zicbop_zicboz
+kernel-cflags += -march=rv64imafdcbv_zicsr_zicntr_zihpm_zba_zbb_zbs_zihintpause_zicbom_zicbop_zicboz_zifencei
 target-qemuflags = --machine virt --cpu rva22s64 --smp 8 -m 4G