Module Instantiation and Align

[rickydtran]

Issues:
Module Instantiation ignores generic mapping.
Labels within a block statement don't have syntax highlighting (color, i don't know what it's specifically called)

Possible Additions:
Control label names of module being instantiated
For instantiating and aligning, look for =>(space) and then put a comma.
Then port map the signals by looking for =>(space) and replace with =>(space)(signal name)

Personally I like manually hooking up the signals for a bit more control, and to know what discrete signals that I'm adding and where I add them. Might be cool if there was another instantiating option that did a snippet with everything, but the actual mappings of the entity or prompt if I want to auto port map.

I also forked your project, but I'm by no means a guru of creating Sublime Packages, but since I'm currently using this as my daily driver at work (I'm not a big fan of bloated IDE's like Sigasi), I could try to help or at least look for where it could be improved.

[TheClams]

Module instantiation works for generic, at least on the code I use: can you provide an example where it does not ?

There is already some option to control the auto-connection and the instance name (Preference-> Packaeg Settings -> SmartVHDL -> Settings), but I can add something intermediate that would work like a snippets.

[rickydtran]

Oh I wasn't aware of the Package Settings. As for the generics not coming up, the rtl generally looks like
generic(
IS_SIMULATION : natural
);
port(

);

[TheClams]

The issue was related to the missing default value, so this is now supported.
I added an option vhdl.instance_as_snippet to allow instantiating the module as a snippets so you can enter each port name manually and the instance name.
Currently this is not compatible with signal declaration, I'll add that later