Merge branch 'steveicarus:master' into master

Author: akashlevy

Documentation/conf.py

@@ -142,7 +142,7 @@
 # One entry per manual page. List of tuples
 # (source start file, name, description, authors, manual section).
 man_pages = [
-    (master_doc, 'icarusverilog', 'Icarus Verilog Documentation',
+    (master_doc, 'iverilog-docs', 'Icarus Verilog Documentation',
      [author], 1)
 ]
 

iverilog-vpi.sh

@@ -1,5 +1,7 @@
 #!/bin/sh
 #
+# Copyright (c) 1998-2026 Stephen Williams (steve@icarus.com)
+#
 #    This source code is free software; you can redistribute it
 #    and/or modify it in source code form under the terms of the GNU
 #    Library General Public License as published by the Free Software

ivtest/fpga_tests/fpga_reg.sh

@@ -1,5 +1,6 @@
 #!/bin/sh
 
+# Copyright (c) 1998-2026 Stephen Williams (steve@icarus.com)
 #
 #    This source code is free software; you can redistribute it
 #    and/or modify it in source code form under the terms of the GNU

vpi/fstapi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2023 Tony Bybell.
+ * Copyright (c) 2009-2026 Tony Bybell.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -3203,7 +3203,8 @@ static const char *modtypes[] = {"module",
                                  "vhdl_for_generate",
                                  "vhdl_if_generate",
                                  "vhdl_generate",
-                                 "vhdl_package"};
+                                 "vhdl_package",
+                                 "unpacked"};
 
 static const char *attrtypes[] = {"misc", "array", "enum", "class"};
 

vpi/fstapi.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2018 Tony Bybell.
+ * Copyright (c) 2009-2026 Tony Bybell.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -108,7 +108,8 @@ enum fstScopeType
     FST_ST_VHDL_GENERATE = 20,
     FST_ST_VHDL_PACKAGE = 21,
 
-    FST_ST_MAX = 21,
+    FST_ST_UNPACKED_DIM = 22,
+    FST_ST_MAX = 22,
 
     FST_ST_GEN_ATTRBEGIN = 252,
     FST_ST_GEN_ATTREND = 253,