AES/InvMix.v.bak at main · Safan05/AES · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
module InvMix(input[0:127] in_state,output[0:127] out_state);
wire[0:7] ewire =8'h0e;
wire[0:7] dwire =8'h0d;
wire[0:7] bwire =8'h0b;
wire[0:7] wire9 =8'h09;

//function[0:7] multiply_2(input[0:7] in_byte,input integer n);
//integer i;
//begin
//for(i = 0;i < n; i=i+1) begin
// in_byte = {in_byte[1:7], in_byte[0]};
//  if(in_byte[0])
//    in_byte = in_byte ^ 8'h1b;
//end
//multiply_2 = in_byte;
//end
//endfunction
function automatic [0:7] multiply_2(input[0:7] in_byte,input integer n);
integer i;
begin
for(i = 0;i < n; i=i+1) begin
  if(in_byte[0]) begin
      in_byte = {in_byte[1:7], 1'b0} ^ (8'h1b & {8{in_byte[0]}});
   end
else in_byte = {in_byte[1:7],in_byte[0]};
end
multiply_2 = in_byte;
end
endfunction

function[0:7] product(input[0:7] i_byte,input[0:7] element);
begin
     if(element == 8'h0e) begin
        product = multiply_2(i_byte,3) ^ multiply_2(i_byte,2) ^ multiply_2(i_byte,1);
end

else if(element == 8'h0b) begin
        product = multiply_2(i_byte,3) ^ multiply_2(i_byte,1) ^ i_byte;
end

else if(element == 8'h0d) begin
        product = multiply_2(i_byte,3) ^ multiply_2(i_byte,2) ^ i_byte;
end

else if(element == 8'h09) begin
       product = multiply_2(i_byte,3) ^ i_byte;
end
end
endfunction

//assigning multiply
//reg[0:7] b;
//initial begin
//b = multiply_2 (a[0:7],4);
//end

genvar i;
generate
for(i=0;i<4;i=i+1) begin: multi
//wrong copyfrom site
//assign out_state[(i*32 + 24)+:8] = product(in_state[(i*32 + 24)+:8],ewire) ^  product(in_state[(i*32 + 16)+:8],bwire) ^ product(in_state[(i*32 + 8)+:8],dwire) ^ product(in_state[i*32+:8],wire9);
//assign out_state[(i*32 + 16)+:8] = product(in_state[(i*32 + 24)+:8],wire9) ^  product(in_state[(i*32 + 16)+:8],wire9) ^ product(in_state[(i*32 + 8)+:8],bwire) ^ product(in_state[i*32+:8],dwire);
//assign out_state[(i*32 + 16)+:8] = product(in_state[(i*32 + 24)+:8],dwire) ^  product(in_state[(i*32 + 16)+:8],wire9) ^ product(in_state[(i*32 + 8)+:8],ewire) ^ product(in_state[i*32+:8],bwire);
//assign out_state[i*32+:8]        = product(in_state[(i*32 + 24)+:8],bwire) ^  product(in_state[(i*32 + 16)+:8],dwire) ^ product(in_state[(i*32 + 8)+:8],wire9) ^ product(in_state[i*32+:8],ewire);

//right copy if slice works
//assign out_state[i*32 + :8]      = product(in_state[(i*32)+:8],ewire) ^  product(in_state[(i*32 +8)+:8],bwire) ^ product(in_state[(i*32 + 16)+:8],dwire) ^ product(in_state[(i*32 + 24)+:8],wire9);
//assign out_state[(i*32 + 8):8]   = product(in_state[(i*32)+:8],wire9) ^  product(in_state[(i*32 +8)+:8],ewire) ^ product(in_state[(i*32 + 16)+:8],bwire) ^ product(in_state[(i*32 + 24)+:8],dwire);
//assign out_state[(i*32 + 16):8]  = product(in_state[(i*32)+:8],dwire) ^  product(in_state[(i*32 +8)+:8],wire9) ^ product(in_state[(i*32 + 16)+:8],ewire) ^ product(in_state[(i*32 + 24)+:8],bwire);
//assign out_state[(i*32 + 24):8]  = product(in_state[(i*32)+:8],bwire) ^  product(in_state[(i*32 +8)+:8],dwire) ^ product(in_state[(i*32 + 16)+:8],wire9) ^ product(in_state[(i*32 + 24)+:8],ewire);


//write index myself
//assign out_state[i*32 :(i*32)+8]      = product(in_state[(i*32)+:8],ewire) ^  product(in_state[(i*32 +8)+:8],bwire) ^ product(in_state[(i*32 + 16)+:8],dwire) ^ product(in_state[(i*32 + 24)+:8],wire9);
//assign out_state[(i*32 + 8):(i*32 + 8)+8]   = product(in_state[(i*32)+:8],wire9) ^  product(in_state[(i*32 +8)+:8],ewire) ^ product(in_state[(i*32 + 16)+:8],bwire) ^ product(in_state[(i*32 + 24)+:8],dwire);
//assign out_state[(i*32 + 16):(i*32 + 16)+8]  = product(in_state[(i*32)+:8],dwire) ^  product(in_state[(i*32 +8)+:8],wire9) ^ product(in_state[(i*32 + 16)+:8],ewire) ^ product(in_state[(i*32 + 24)+:8],bwire);
//assign out_state[(i*32 + 24):(i*32 + 24)+8]  = product(in_state[(i*32)+:8],bwire) ^  product(in_state[(i*32 +8)+:8],dwire) ^ product(in_state[(i*32 + 16)+:8],wire9) ^ product(in_state[(i*32 + 24)+:8],ewire);
//
 assign out_state[(i*32) +:8]    = product(in_state[(i*32)+:8],ewire) ^  product(in_state[(i*32 +8)+:8],bwire) ^ product(in_state[(i*32 + 16)+:8],dwire) ^ product(in_state[(i*32 + 24)+:8],wire9);
  assign out_state[(i*32 + 8)+:8]   = product(in_state[(i*32)+:8],wire9) ^  product(in_state[(i*32 +8)+:8],ewire) ^ product(in_state[(i*32 + 16)+:8],bwire) ^ product(in_state[(i*32 + 24)+:8],dwire);
  assign out_state[(i*32 + 16)+:8]  = product(in_state[(i*32)+:8],dwire) ^  product(in_state[(i*32 +8)+:8],wire9) ^ product(in_state[(i*32 + 16)+:8],ewire) ^ product(in_state[(i*32 + 24)+:8],bwire);
  assign out_state[(i*32 + 24)+:8]  = product(in_state[(i*32)+:8],bwire) ^  product(in_state[(i*32 +8)+:8],dwire) ^ product(in_state[(i*32 + 16)+:8],wire9) ^ product(in_state[(i*32 + 24)+:8],ewire);
end
endgenerate


//initial begin
//test = product(in_test,ewire);
//end

endmodule