decimation

[peepo]

Hi there,

is this: https://github.com/Roboy/iceboard/blob/master/software/adc_lvds/verilog/cic.v
working code?

Two queries:
1] data_in <= diff_input; but one is wire the other [7:0] which might not normally be intentional?
perhaps data_in <= integrator; // as against current data_out <= integrator; when cic not in use?
ie what am I not understanding?

2] output d_clk is not currently connected. Does it have an essential purpose?

thanks for any guidance!!

I need a CIC module for ADC and there are few available