|
4 | 4 | * SPDX-License-Identifier: Apache-2.0 |
5 | 5 | * |
6 | 6 | * Change Logs: |
7 | | - * Date Author Notes |
8 | | - * 2024-02-06 Dyyt587 first version |
9 | | - * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG |
10 | | - * 2024-06-23 wdfk-prog Add H7 hard I2C config |
| 7 | + * Date Author Notes |
| 8 | + * 2026-06-07 dirtwillfly first version for NS800 |
11 | 9 | */ |
12 | 10 | #ifndef __I2C_HARD_CONFIG_H__ |
13 | 11 | #define __I2C_HARD_CONFIG_H__ |
|
18 | 16 | extern "C" { |
19 | 17 | #endif |
20 | 18 |
|
| 19 | +/* I2C1 default GPIO configuration */ |
| 20 | +/* GPIO_0 (SDA) -> GPIOA, GPIO_PIN_0 */ |
| 21 | +/* GPIO_1 (SCL) -> GPIOA, GPIO_PIN_1 */ |
| 22 | +#ifndef BSP_I2C1_SCL_PIN_NUM |
| 23 | +#define BSP_I2C1_SCL_PIN_NUM 1U |
| 24 | +#endif |
| 25 | +#ifndef BSP_I2C1_SDA_PIN_NUM |
| 26 | +#define BSP_I2C1_SDA_PIN_NUM 0U |
| 27 | +#endif |
| 28 | +#ifndef BSP_I2C1_SCL_PORT |
| 29 | +#define BSP_I2C1_SCL_PORT GPIOA |
| 30 | +#endif |
| 31 | +#ifndef BSP_I2C1_SDA_PORT |
| 32 | +#define BSP_I2C1_SDA_PORT GPIOA |
| 33 | +#endif |
| 34 | +#ifndef BSP_I2C1_SCL_PIN |
| 35 | +#define BSP_I2C1_SCL_PIN GPIO_PIN_1 |
| 36 | +#endif |
| 37 | +#ifndef BSP_I2C1_SDA_PIN |
| 38 | +#define BSP_I2C1_SDA_PIN GPIO_PIN_0 |
| 39 | +#endif |
| 40 | +#ifndef BSP_I2C1_SCL_ALT_FUNC |
| 41 | +#define BSP_I2C1_SCL_ALT_FUNC ALT6_FUNCTION |
| 42 | +#endif |
| 43 | +#ifndef BSP_I2C1_SDA_ALT_FUNC |
| 44 | +#define BSP_I2C1_SDA_ALT_FUNC ALT6_FUNCTION |
| 45 | +#endif |
| 46 | + |
| 47 | +/* I2C2 default GPIO configuration */ |
| 48 | +/* GPIO_34 (SDA) -> GPIOB, GPIO_PIN_2 */ |
| 49 | +/* GPIO_35 (SCL) -> GPIOB, GPIO_PIN_3 */ |
| 50 | +#ifndef BSP_I2C2_SCL_PIN_NUM |
| 51 | +#define BSP_I2C2_SCL_PIN_NUM 35U |
| 52 | +#endif |
| 53 | +#ifndef BSP_I2C2_SDA_PIN_NUM |
| 54 | +#define BSP_I2C2_SDA_PIN_NUM 34U |
| 55 | +#endif |
| 56 | +#ifndef BSP_I2C2_SCL_PORT |
| 57 | +#define BSP_I2C2_SCL_PORT GPIOB |
| 58 | +#endif |
| 59 | +#ifndef BSP_I2C2_SDA_PORT |
| 60 | +#define BSP_I2C2_SDA_PORT GPIOB |
| 61 | +#endif |
| 62 | +#ifndef BSP_I2C2_SCL_PIN |
| 63 | +#define BSP_I2C2_SCL_PIN GPIO_PIN_3 |
| 64 | +#endif |
| 65 | +#ifndef BSP_I2C2_SDA_PIN |
| 66 | +#define BSP_I2C2_SDA_PIN GPIO_PIN_2 |
| 67 | +#endif |
| 68 | +#ifndef BSP_I2C2_SCL_ALT_FUNC |
| 69 | +#define BSP_I2C2_SCL_ALT_FUNC ALT6_FUNCTION |
| 70 | +#endif |
| 71 | +#ifndef BSP_I2C2_SDA_ALT_FUNC |
| 72 | +#define BSP_I2C2_SDA_ALT_FUNC ALT6_FUNCTION |
| 73 | +#endif |
| 74 | + |
21 | 75 | #ifdef BSP_USING_HARD_I2C1 |
| 76 | +#ifndef BSP_I2C1_BAUDRATE |
| 77 | +#define BSP_I2C1_BAUDRATE 100000 |
| 78 | +#endif |
| 79 | + |
22 | 80 | #ifndef I2C1_BUS_CONFIG |
23 | | -#define I2C1_BUS_CONFIG \ |
24 | | - { \ |
25 | | - .Instance = I2C1, \ |
26 | | - .timing = 0x307075B1, \ |
27 | | - .timeout = 1000, \ |
28 | | - .name = "hwi2c1", \ |
29 | | - .evirq_type = I2C1_EV_IRQn, \ |
30 | | - .erirq_type = I2C1_ER_IRQn, \ |
| 81 | +#define I2C1_BUS_CONFIG \ |
| 82 | + { \ |
| 83 | + .name = "hwi2c1", \ |
| 84 | + .Instance = I2C1, \ |
| 85 | + .baudrate = BSP_I2C1_BAUDRATE, \ |
| 86 | + .timeout = 1000, \ |
| 87 | + .irq_type = I2C1_MST_IRQn, \ |
| 88 | + .scl_pin_num = BSP_I2C1_SCL_PIN_NUM, \ |
| 89 | + .sda_pin_num = BSP_I2C1_SDA_PIN_NUM, \ |
| 90 | + .scl_port = BSP_I2C1_SCL_PORT, \ |
| 91 | + .sda_port = BSP_I2C1_SDA_PORT, \ |
| 92 | + .scl_pin = BSP_I2C1_SCL_PIN, \ |
| 93 | + .sda_pin = BSP_I2C1_SDA_PIN, \ |
| 94 | + .scl_alt_func = BSP_I2C1_SCL_ALT_FUNC, \ |
| 95 | + .sda_alt_func = BSP_I2C1_SDA_ALT_FUNC, \ |
31 | 96 | } |
32 | 97 | #endif /* I2C1_BUS_CONFIG */ |
33 | 98 | #endif /* BSP_USING_HARD_I2C1 */ |
34 | 99 |
|
35 | | -#ifdef BSP_I2C1_TX_USING_DMA |
36 | | -#ifndef I2C1_TX_DMA_CONFIG |
37 | | -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) |
38 | | -#define I2C1_TX_DMA_CONFIG \ |
39 | | - { \ |
40 | | - .dma_rcc = I2C1_TX_DMA_RCC, \ |
41 | | - .Instance = I2C1_TX_DMA_INSTANCE, \ |
42 | | - .dma_irq = I2C1_TX_DMA_IRQ, \ |
43 | | - .channel = I2C1_TX_DMA_CHANNEL \ |
44 | | - } |
45 | | -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) |
46 | | -#define I2C1_TX_DMA_CONFIG \ |
47 | | - { \ |
48 | | - .dma_rcc = I2C1_TX_DMA_RCC, \ |
49 | | - .Instance = I2C1_TX_DMA_INSTANCE, \ |
50 | | - .dma_irq = I2C1_TX_DMA_IRQ, \ |
51 | | - .request = DMA_REQUEST_I2C1_TX \ |
52 | | - } |
53 | | -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ |
54 | | -#endif /* I2C1_TX_DMA_CONFIG */ |
55 | | -#endif /* BSP_I2C1_TX_USING_DMA */ |
56 | | - |
57 | | -#ifdef BSP_I2C1_RX_USING_DMA |
58 | | -#ifndef I2C1_RX_DMA_CONFIG |
59 | | -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) |
60 | | -#define I2C1_RX_DMA_CONFIG \ |
61 | | - { \ |
62 | | - .dma_rcc = I2C1_RX_DMA_RCC, \ |
63 | | - .Instance = I2C1_RX_DMA_INSTANCE, \ |
64 | | - .dma_irq = I2C1_RX_DMA_IRQ, \ |
65 | | - .channel = I2C1_RX_DMA_CHANNEL, \ |
66 | | - } |
67 | | -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) |
68 | | -#define I2C1_RX_DMA_CONFIG \ |
69 | | - { \ |
70 | | - .dma_rcc = I2C1_RX_DMA_RCC, \ |
71 | | - .Instance = I2C1_RX_DMA_INSTANCE, \ |
72 | | - .dma_irq = I2C1_RX_DMA_IRQ, \ |
73 | | - .request = DMA_REQUEST_I2C1_RX \ |
74 | | - } |
75 | | -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ |
76 | | -#endif /* I2C1_RX_DMA_CONFIG */ |
77 | | -#endif /* BSP_I2C1_RX_USING_DMA */ |
78 | | - |
79 | 100 | #ifdef BSP_USING_HARD_I2C2 |
| 101 | +#ifndef BSP_I2C2_BAUDRATE |
| 102 | +#define BSP_I2C2_BAUDRATE 100000 |
| 103 | +#endif |
| 104 | + |
80 | 105 | #ifndef I2C2_BUS_CONFIG |
81 | | -#define I2C2_BUS_CONFIG \ |
82 | | - { \ |
83 | | - .Instance = I2C2, \ |
84 | | - .timing = 0x307075B1, \ |
85 | | - .timeout = 1000, \ |
86 | | - .name = "hwi2c2", \ |
87 | | - .evirq_type = I2C2_EV_IRQn, \ |
88 | | - .erirq_type = I2C2_ER_IRQn, \ |
| 106 | +#define I2C2_BUS_CONFIG \ |
| 107 | + { \ |
| 108 | + .name = "hwi2c2", \ |
| 109 | + .Instance = I2C2, \ |
| 110 | + .baudrate = BSP_I2C2_BAUDRATE, \ |
| 111 | + .timeout = 1000, \ |
| 112 | + .irq_type = I2C2_MST_IRQn, \ |
| 113 | + .scl_pin_num = BSP_I2C2_SCL_PIN_NUM, \ |
| 114 | + .sda_pin_num = BSP_I2C2_SDA_PIN_NUM, \ |
| 115 | + .scl_port = BSP_I2C2_SCL_PORT, \ |
| 116 | + .sda_port = BSP_I2C2_SDA_PORT, \ |
| 117 | + .scl_pin = BSP_I2C2_SCL_PIN, \ |
| 118 | + .sda_pin = BSP_I2C2_SDA_PIN, \ |
| 119 | + .scl_alt_func = BSP_I2C2_SCL_ALT_FUNC, \ |
| 120 | + .sda_alt_func = BSP_I2C2_SDA_ALT_FUNC, \ |
89 | 121 | } |
90 | 122 | #endif /* I2C2_BUS_CONFIG */ |
91 | 123 | #endif /* BSP_USING_HARD_I2C2 */ |
92 | 124 |
|
93 | | -#ifdef BSP_I2C2_TX_USING_DMA |
94 | | -#ifndef I2C2_TX_DMA_CONFIG |
95 | | -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) |
96 | | -#define I2C2_TX_DMA_CONFIG \ |
97 | | - { \ |
98 | | - .dma_rcc = I2C2_TX_DMA_RCC, \ |
99 | | - .Instance = I2C2_TX_DMA_INSTANCE, \ |
100 | | - .dma_irq = I2C2_TX_DMA_IRQ, \ |
101 | | - .channel = I2C2_TX_DMA_CHANNEL, \ |
102 | | - } |
103 | | -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) |
104 | | -#define I2C2_TX_DMA_CONFIG \ |
105 | | - { \ |
106 | | - .dma_rcc = I2C2_TX_DMA_RCC, \ |
107 | | - .Instance = I2C2_TX_DMA_INSTANCE, \ |
108 | | - .dma_irq = I2C2_TX_DMA_IRQ, \ |
109 | | - .request = DMA_REQUEST_I2C2_TX \ |
110 | | - } |
111 | | -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ |
112 | | -#endif /* I2C2_TX_DMA_CONFIG */ |
113 | | -#endif /* BSP_I2C2_TX_USING_DMA */ |
114 | | - |
115 | | -#ifdef BSP_I2C2_RX_USING_DMA |
116 | | -#ifndef I2C2_RX_DMA_CONFIG |
117 | | -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) |
118 | | -#define I2C2_RX_DMA_CONFIG \ |
119 | | - { \ |
120 | | - .dma_rcc = I2C2_RX_DMA_RCC, \ |
121 | | - .Instance = I2C2_RX_DMA_INSTANCE, \ |
122 | | - .dma_irq = I2C2_RX_DMA_IRQ, \ |
123 | | - .channel = I2C2_RX_DMA_CHANNEL, \ |
124 | | - } |
125 | | -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) |
126 | | -#define I2C2_RX_DMA_CONFIG \ |
127 | | - { \ |
128 | | - .dma_rcc = I2C2_RX_DMA_RCC, \ |
129 | | - .Instance = I2C2_RX_DMA_INSTANCE, \ |
130 | | - .dma_irq = I2C2_RX_DMA_IRQ, \ |
131 | | - .request = DMA_REQUEST_I2C2_RX \ |
132 | | - } |
133 | | -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ |
134 | | -#endif /* I2C2_RX_DMA_CONFIG */ |
135 | | -#endif /* BSP_I2C2_RX_USING_DMA */ |
136 | | - |
137 | | -#ifdef BSP_USING_HARD_I2C3 |
138 | | -#ifndef I2C3_BUS_CONFIG |
139 | | -#define I2C3_BUS_CONFIG \ |
140 | | - { \ |
141 | | - .Instance = I2C3, \ |
142 | | - .timing = 0x307075B1, \ |
143 | | - .timeout = 1000, \ |
144 | | - .name = "hwi2c3", \ |
145 | | - .evirq_type = I2C3_EV_IRQn, \ |
146 | | - .erirq_type = I2C3_ER_IRQn, \ |
147 | | - } |
148 | | -#endif /* I2C3_BUS_CONFIG */ |
149 | | -#endif /* BSP_USING_HARD_I2C3 */ |
150 | | - |
151 | | -#ifdef BSP_I2C3_TX_USING_DMA |
152 | | -#ifndef I2C3_TX_DMA_CONFIG |
153 | | -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) |
154 | | -#define I2C3_TX_DMA_CONFIG \ |
155 | | - { \ |
156 | | - .dma_rcc = I2C3_TX_DMA_RCC, \ |
157 | | - .Instance = I2C3_TX_DMA_INSTANCE, \ |
158 | | - .dma_irq = I2C3_TX_DMA_IRQ, \ |
159 | | - .channel = I2C3_TX_DMA_CHANNEL, \ |
160 | | - } |
161 | | -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) |
162 | | -#define I2C3_TX_DMA_CONFIG \ |
163 | | - { \ |
164 | | - .dma_rcc = I2C3_TX_DMA_RCC, \ |
165 | | - .Instance = I2C3_TX_DMA_INSTANCE, \ |
166 | | - .dma_irq = I2C3_TX_DMA_IRQ, \ |
167 | | - .request = DMA_REQUEST_I2C3_TX \ |
168 | | - } |
169 | | -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ |
170 | | -#endif /* I2C3_TX_DMA_CONFIG */ |
171 | | -#endif /* BSP_I2C3_TX_USING_DMA */ |
172 | | - |
173 | | -#ifdef BSP_I2C3_RX_USING_DMA |
174 | | -#ifndef I2C3_RX_DMA_CONFIG |
175 | | -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) |
176 | | -#define I2C3_RX_DMA_CONFIG \ |
177 | | - { \ |
178 | | - .dma_rcc = I2C3_RX_DMA_RCC, \ |
179 | | - .Instance = I2C3_RX_DMA_INSTANCE, \ |
180 | | - .dma_irq = I2C3_RX_DMA_IRQ, \ |
181 | | - .channel = I2C3_RX_DMA_CHANNEL, \ |
182 | | - } |
183 | | -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) |
184 | | -#define I2C3_RX_DMA_CONFIG \ |
185 | | - { \ |
186 | | - .dma_rcc = I2C3_RX_DMA_RCC, \ |
187 | | - .Instance = I2C3_RX_DMA_INSTANCE, \ |
188 | | - .dma_irq = I2C3_RX_DMA_IRQ, \ |
189 | | - .request = DMA_REQUEST_I2C3_RX \ |
190 | | - } |
191 | | -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ |
192 | | -#endif /* I2C3_RX_DMA_CONFIG */ |
193 | | -#endif /* BSP_I2C3_RX_USING_DMA */ |
194 | | - |
195 | | -#ifdef BSP_USING_HARD_I2C4 |
196 | | -#ifndef I2C4_BUS_CONFIG |
197 | | -#define I2C4_BUS_CONFIG \ |
198 | | - { \ |
199 | | - .Instance = I2C4, \ |
200 | | - .timing = 0x307075B1, \ |
201 | | - .timeout = 1000, \ |
202 | | - .name = "hwi2c4", \ |
203 | | - .evirq_type = I2C4_EV_IRQn, \ |
204 | | - .erirq_type = I2C4_ER_IRQn, \ |
205 | | - } |
206 | | -#endif /* I2C4_BUS_CONFIG */ |
207 | | -#endif /* BSP_USING_HARD_I2C4 */ |
208 | | - |
209 | | -#ifdef BSP_I2C4_TX_USING_DMA |
210 | | -#ifndef I2C4_TX_DMA_CONFIG |
211 | | -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) |
212 | | -#define I2C4_TX_DMA_CONFIG \ |
213 | | - { \ |
214 | | - .dma_rcc = I2C4_TX_DMA_RCC, \ |
215 | | - .Instance = I2C4_TX_DMA_INSTANCE, \ |
216 | | - .dma_irq = I2C4_TX_DMA_IRQ, \ |
217 | | - .channel = I2C4_TX_DMA_CHANNEL, \ |
218 | | - } |
219 | | -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) |
220 | | -#define I2C4_TX_DMA_CONFIG \ |
221 | | - { \ |
222 | | - .dma_rcc = I2C4_TX_DMA_RCC, \ |
223 | | - .Instance = I2C4_TX_DMA_INSTANCE, \ |
224 | | - .dma_irq = I2C4_TX_DMA_IRQ, \ |
225 | | - .request = DMA_REQUEST_I2C4_TX \ |
226 | | - } |
227 | | -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ |
228 | | -#endif /* I2C4_TX_DMA_CONFIG */ |
229 | | -#endif /* BSP_I2C4_TX_USING_DMA */ |
230 | | - |
231 | | -#ifdef BSP_I2C4_RX_USING_DMA |
232 | | -#ifndef I2C4_RX_DMA_CONFIG |
233 | | -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) |
234 | | -#define I2C4_RX_DMA_CONFIG \ |
235 | | - { \ |
236 | | - .dma_rcc = I2C4_RX_DMA_RCC, \ |
237 | | - .Instance = I2C4_RX_DMA_INSTANCE, \ |
238 | | - .dma_irq = I2C4_RX_DMA_IRQ, \ |
239 | | - .channel = I2C4_RX_DMA_CHANNEL, \ |
240 | | - } |
241 | | -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) |
242 | | -#define I2C4_RX_DMA_CONFIG \ |
243 | | - { \ |
244 | | - .dma_rcc = I2C4_RX_DMA_RCC, \ |
245 | | - .Instance = I2C4_RX_DMA_INSTANCE, \ |
246 | | - .dma_irq = I2C4_RX_DMA_IRQ, \ |
247 | | - .request = DMA_REQUEST_I2C4_RX \ |
248 | | - } |
249 | | -#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ |
250 | | -#endif /* I2C4_RX_DMA_CONFIG */ |
251 | | -#endif /* BSP_I2C4_RX_USING_DMA */ |
252 | | - |
253 | | - |
254 | 125 | #ifdef __cplusplus |
255 | 126 | } |
256 | 127 | #endif |
257 | 128 |
|
258 | | -#endif /*__I2C_HARD_CONFIG_H__ */ |
| 129 | +#endif /* __I2C_HARD_CONFIG_H__ */ |
259 | 130 |
|
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