feat[ADC]: 新增 ADC V2 驱动支持 (#11440)

* feat[ADC V2]: add ADC V2 driver support

add ADC V2 core APIs, session state management, and sequence read support
add STM32 ADC V2 HAL backend with internal-channel and VREF handling
add per-series STM32 ADC V2 default configuration headers
wire ADC V2 Kconfig and SConscript integration for components and STM32 BSP drivers
keep ADC V2 mutually exclusive with the legacy ADC driver path

* feat[ADC V2]: add ADC V2 MSH special channel read support

add generic ADC V2 MSH commands for probing, configuring, raw reads, voltage reads, and sequence reads
add STM32 ADC V2 backend special commands for VREFINT, temperature sensor, and VBAT reads
add STM32 helper APIs for special logical channels, sampling time, resolution, and temperature calculation
wire ADC V2 MSH sources through Kconfig and SConscript

* feat[ADC V2]: add ADC V2 stream DMA support

add ADC V2 stream APIs with latest-frame and FIFO buffering policies
wire STM32 ADC V2 to circular DMA stream mode with per-instance Kconfig options
extend STM32 ADC config headers and DMA helpers for stream DMA configuration
add FinSH stream commands for start, read, cancel, and stop operations
handle Cortex-M7 cache-safe DMA buffers for STM32 stream sampling

* feat[ADC V2]: add timer trigger support for ADC V2 streams

add ADC V2 trigger configuration, validation, and lifecycle coordination
add timer update trigger support through clock timer TRGO controls
map STM32 ADC V2 timer update triggers to HAL external trigger selector fields
add Kconfig, SConscript, and MSH entries for ADC trigger setup and inspection

* feat[ADCV2]: add timer and comparator trigger selectors

add ADC V2 timer compare and analog comparator trigger configuration support
extend clock timer trigger config with compare event and channel fields
wire STM32 ADC external trigger selector mappings for TIM update, TIM compare, and COMP output
add FinSH trigger_set commands and Kconfig switches for timer and comparator trigger backends

* fix[ADC V2]: resolve ADC V1 compatibility Kconfig loop

* ci[ADC V2][stm32]: add ADC v2 peripheral config for stm32f407-rt-spark BSP

Author: wdfk-prog

bsp/stm32/libraries/HAL_Drivers/drivers/Kconfig

@@ -24,6 +24,116 @@ if BSP_USING_USBD
         # "ULPI: UTMI+ Low Pin Interface"
 endif
 
+menuconfig BSP_USING_ADC_V2
+    bool "Enable ADC V2"
+    select RT_USING_ADC
+    select RT_USING_ADC_V2
+    default n
+
+if BSP_USING_ADC_V2
+    config BSP_USING_ADC1
+        bool "Enable ADC1"
+        default n
+
+    config BSP_USING_ADC2
+        bool "Enable ADC2"
+        depends on (SOC_SERIES_STM32F1 || SOC_SERIES_STM32F2 || SOC_SERIES_STM32F3 || \
+                    SOC_SERIES_STM32F4 || SOC_SERIES_STM32G4 || SOC_SERIES_STM32F7 || \
+                    SOC_SERIES_STM32H5 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32H7RS || \
+                    SOC_SERIES_STM32L4 || SOC_SERIES_STM32L5 || SOC_SERIES_STM32MP1 || \
+                    SOC_SERIES_STM32U5)
+        default n
+
+    config BSP_USING_ADC3
+        bool "Enable ADC3"
+        depends on (SOC_SERIES_STM32F1 || SOC_SERIES_STM32F2 || SOC_SERIES_STM32F3 || \
+                    SOC_SERIES_STM32F4 || SOC_SERIES_STM32G4 || SOC_SERIES_STM32F7 || \
+                    SOC_SERIES_STM32H7 || SOC_SERIES_STM32L4 || SOC_SERIES_STM32MP1)
+        default n
+
+    config BSP_USING_ADC4
+        bool "Enable ADC4"
+        depends on (SOC_SERIES_STM32F3 || SOC_SERIES_STM32G4 || SOC_SERIES_STM32U5)
+        default n
+
+    config BSP_ADC_USING_TRIGGER
+        bool "Enable ADC V2 trigger backend"
+        select RT_ADC_USING_TRIGGER
+        default n
+        help
+            Enable STM32 ADC V2 trigger selector validation and backend
+            encoding. The ADC backend maps the framework-cached trigger to STM32
+            HAL ADC selector fields. Trigger-source frequency and lifecycle are
+            owned by the ADC trigger framework and timer trigger backend.
+
+    config BSP_ADC_USING_TIMER_TRIGGER
+        bool "Enable ADC V2 timer trigger selector backend"
+        depends on BSP_ADC_USING_TRIGGER
+        depends on BSP_USING_TIM
+        depends on RT_USING_CLOCK_TIME
+        select RT_ADC_TRIGGER_USING_TIMER
+        select RT_USING_CLOCK_TIMER_TRIGGER
+        default n
+        help
+            Enable STM32 TIMx update/TRGO and compare event to ADC external
+            trigger selector mapping for ADC V2 stream pacing. Timer frequency,
+            TRGO/compare setup, and lifecycle are handled through the clock
+            timer trigger backend during ADC stream start and stop.
+
+    config BSP_ADC_USING_ANALOG_COMPARE_TRIGGER
+        bool "Enable ADC V2 analog comparator trigger selector backend"
+        depends on BSP_ADC_USING_TRIGGER
+        select RT_ADC_TRIGGER_USING_COMPARE
+        default n
+        help
+            Enable STM32 COMPx_OUT to ADC external trigger selector mapping for
+            ADC V2. Comparator input, threshold, polarity, and enable state are
+            owned by board code, application code, or a comparator driver.
+
+    config BSP_ADC_USING_STREAM_DMA
+        bool
+
+    config BSP_ADC1_USING_DMA
+        bool "Enable ADC1 stream DMA backend"
+        depends on BSP_USING_ADC1
+        select RT_ADC_USING_STREAM
+        select BSP_ADC_USING_STREAM_DMA
+        default n
+        help
+            Enable the STM32 ADC1 DMA backend for ADC V2 stream sessions.
+
+            This option only enables the board-level DMA backend. The stream
+            framework and buffering policies are controlled by RT_ADC_USING_STREAM,
+            RT_ADC_STREAM_USING_LATEST, and RT_ADC_STREAM_USING_FIFO.
+
+    config BSP_ADC2_USING_DMA
+        bool "Enable ADC2 stream DMA backend"
+        depends on BSP_USING_ADC2
+        select RT_ADC_USING_STREAM
+        select BSP_ADC_USING_STREAM_DMA
+        default n
+        help
+            Enable the STM32 ADC2 DMA backend for ADC V2 stream sessions.
+
+    config BSP_ADC3_USING_DMA
+        bool "Enable ADC3 stream DMA backend"
+        depends on BSP_USING_ADC3
+        select RT_ADC_USING_STREAM
+        select BSP_ADC_USING_STREAM_DMA
+        default n
+        help
+            Enable the STM32 ADC3 DMA backend for ADC V2 stream sessions.
+
+    config BSP_ADC4_USING_DMA
+        bool "Enable ADC4 stream DMA backend"
+        depends on BSP_USING_ADC4
+        select RT_ADC_USING_STREAM
+        select BSP_ADC_USING_STREAM_DMA
+        default n
+        help
+            Enable the STM32 ADC4 DMA backend for ADC V2 stream sessions.
+endif
+
 config BSP_USING_CRC
     bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
     select RT_USING_HWCRYPTO
@@ -59,4 +169,3 @@ config BSP_USING_UDID
     bool "Enable UDID (Unique Device Identifier)"
     select RT_USING_HWCRYPTO
     default n
-

bsp/stm32/libraries/HAL_Drivers/drivers/SConscript

@@ -46,9 +46,18 @@ if GetDepend(['RT_USING_I2C']):
 if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']) and not GetDepend(['SOC_STM32H750_ARTPI']):
     src += ['drv_eth.c']
 
-if GetDepend(['RT_USING_ADC']):
+if GetDepend(['RT_USING_ADC']) and not GetDepend(['RT_USING_ADC_V2']):
     src += ['drv_adc.c']
 
+if GetDepend(['BSP_USING_ADC_V2']):
+    src += ['drv_adc_v2.c']
+
+    if GetDepend(['BSP_ADC_USING_TRIGGER']):
+        src += ['drv_adc_v2_trigger.c']
+
+    if GetDepend(['RT_USING_FINSH', 'RT_ADC_V2_USING_MSH']):
+        src += ['drv_adc_v2_msh.c']
+
 if GetDepend(['RT_USING_DAC']):
     src += ['drv_dac.c']