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Merge pull request #43 from m42uko/feature/diamond
Implement support for Lattice Diamond
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‎README.md‎

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# PyFPGA [![License](https://img.shields.io/badge/License-GPL--3.0-darkgreen?style=flat-square)](LICENSE)
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![Diamond](https://img.shields.io/badge/Diamond-3.13-blue.svg?style=flat-square)
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![ISE](https://img.shields.io/badge/ISE-14.7-blue.svg?style=flat-square)
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![Libero](https://img.shields.io/badge/Libero--Soc-2024.1-blue.svg?style=flat-square)
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![Quartus](https://img.shields.io/badge/Quartus--Prime-23.1-blue.svg?style=flat-square)

‎examples/hooks/diamond.py‎

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"""Diamond example hooks."""
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from pyfpga.diamond import Diamond
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prj = Diamond(odir='../build/diamond')
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hooks = {
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"reports": """
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prj_run Map -task MapTrace -forceOne
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prj_run PAR -task PARTrace -forceOne
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prj_run PAR -task IOTiming -forceOne
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""",
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"netlist_simulation": """
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prj_run Map -task MapVerilogSimFile
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prj_run Map -task MapVHDLSimFile -forceOne
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prj_run Export -task TimingSimFileVHD -forceOne
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prj_run Export -task TimingSimFileVlg -forceOne
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prj_run Export -task IBIS -forceOne
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""",
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"progfile_ecp5u": """
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prj_run Export -task Promgen -forceOne
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""",
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"progfile_machxo2": """
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prj_run Export -task Jedecgen -forceOne
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"""
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}
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prj.set_part('LFXP2-5E-5TN144C')
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prj.add_param('FREQ', '50000000')
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prj.add_param('SECS', '1')
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prj.add_cons('../sources/cons/brevia2/clk.lpf', 'syn')
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prj.add_cons('../sources/cons/brevia2/clk.lpf', 'par')
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prj.add_cons('../sources/cons/brevia2/io.lpf', 'par')
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prj.add_include('../sources/vlog/include1')
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prj.add_include('../sources/vlog/include2')
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prj.add_vlog('../sources/vlog/*.v')
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prj.add_define('DEFINE1', '1')
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prj.add_define('DEFINE2', '1')
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prj.set_top('Top')
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for hook_name, hook in hooks.items():
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prj.add_hook('postpar', hook)
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prj.make()

‎examples/projects/diamond.py‎

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"""Diamond examples."""
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import argparse
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from pyfpga.diamond import Diamond
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parser = argparse.ArgumentParser()
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parser.add_argument(
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'--board', choices=['brevia2'], default='brevia2'
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)
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parser.add_argument(
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'--source', choices=['vlog', 'vhdl', 'slog'], default='vlog'
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)
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parser.add_argument(
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'--action', choices=['make', 'prog', 'all'], default='make'
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)
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args = parser.parse_args()
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prj = Diamond(odir='../build/diamond')
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if args.board == 'brevia2':
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prj.set_part('LFXP2-5E-5TN144C')
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prj.add_param('FREQ', '50000000')
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prj.add_cons('../sources/cons/brevia2/clk.lpf', 'syn')
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prj.add_cons('../sources/cons/brevia2/clk.lpf', 'par')
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prj.add_cons('../sources/cons/brevia2/io.lpf', 'par')
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prj.add_param('SECS', '1')
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if args.source == 'vhdl':
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prj.add_vhdl('../sources/vhdl/*.vhdl', 'blink_lib')
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prj.add_vhdl('../sources/vhdl/top.vhdl')
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if args.source == 'vlog':
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prj.add_include('../sources/vlog/include1')
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prj.add_include('../sources/vlog/include2')
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prj.add_vlog('../sources/vlog/*.v')
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if args.source == 'slog':
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prj.add_include('../sources/slog/include1')
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prj.add_include('../sources/slog/include2')
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prj.add_slog('../sources/slog/*.sv')
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if args.source in ['vlog', 'slog']:
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prj.add_define('DEFINE1', '1')
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prj.add_define('DEFINE2', '1')
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prj.set_top('Top')
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if args.action in ['make', 'all']:
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prj.make()
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if args.action in ['prog', 'all']:
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prj.prog()

‎examples/sources/cons/brevia2/clk.lpf‎

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BLOCK RESETPATHS ;
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BLOCK ASYNCPATHS ;
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FREQUENCY NET "clk_i_c" 50.000000 MHz ;

‎examples/sources/cons/brevia2/io.lpf‎

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LOCATE COMP "clk_i" SITE "21" ;
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IOBUF PORT "clk_i" IO_TYPE=LVCMOS33 ;
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LOCATE COMP "led_o" SITE "37" ;
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IOBUF PORT "led_o" IO_TYPE=LVCMOS33 ;

‎pyfpga/diamond.py‎

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#
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# Copyright (C) 2024 PyFPGA Project
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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Implements support for Diamond.
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"""
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import os
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from pyfpga.project import Project
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class Diamond(Project):
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"""Class to support Diamond projects."""
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def _configure(self):
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tool = 'diamond'
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executable = 'pnmainc' if os.name == 'nt' else 'diamondc'
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self.conf['tool'] = tool
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self.conf['make_cmd'] = f'{executable} {tool}.tcl'
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self.conf['make_ext'] = 'tcl'
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self.conf['prog_bit'] = 'bit'
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self.conf['prog_cmd'] = f'sh {tool}-prog.sh'
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self.conf['prog_ext'] = 'sh'
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def _make_custom(self):
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if 'part' not in self.data:
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self.data['part'] = 'LFXP2-5E-5TN144C'

‎pyfpga/factory.py‎

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# pylint: disable=too-few-public-methods
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from pyfpga.diamond import Diamond
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from pyfpga.ise import Ise
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from pyfpga.libero import Libero
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from pyfpga.openflow import Openflow
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TOOLS = {
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'diamond': Diamond,
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'ise': Ise,
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'libero': Libero,
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'openflow': Openflow,

‎pyfpga/templates/diamond-prog.jinja‎

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{#
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# Copyright (C) 2024 PyFPGA Project
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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#}
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if [ "$DIAMOND_XCF" == "" ]; then
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DIAMOND_XCF=impl1/impl1.xcf
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fi
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if [ -f "$DIAMOND_XCF" ]; then
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pgrcmd -infile $DIAMOND_XCF
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else
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echo "ERROR: Automatic programming with Diamond is not yet supported."
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echo " Please create the `realpath $DIAMOND_XCF` file manually and rerun the prog command."
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echo " Hint: You can change the location of the XCF file by setting the DIAMOND_XCF environment variable."
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exit 1
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fi

‎pyfpga/templates/diamond.jinja‎

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{#
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#
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# Copyright (C) 2015-2024 PyFPGA Project
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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#}
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{% if 'cfg' in steps %}# Project configuration -------------------------------------------------------
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prj_project new -name {{ project }} -dev {{ part }}
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# For now, let's enforce Synplify as LSE (the default) has broken top level generic handling
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prj_syn set synplify
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{% if hooks %}{{ hooks.precfg | join('\n') }}{% endif %}
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{% if files %}# Files inclusion
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{% for name, attr in files.items() %}
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prj_src add {% if 'lib' in attr %}-work {{ attr.lib }}{% else %}{% endif %} {{ name }}
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{% endfor %}
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{% endif %}
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{% if constraints %}
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# Constraints inclusion
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# Diamond only supports one constraints file, so we need to combine them into the default diamond.lpf.
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# We can't just do `prj_src add <constraints-file>` multiple times.
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set fileId [open diamond.lpf "w"]
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{% for name, attr in constraints.items() %}
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set fp [open "{{ name }}" r]
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set file_data [read $fp]
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close $fp
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puts -nonewline $fileId $file_data
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{% endfor %}
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close $fileId
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{% endif %}
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{% if top %}# Top-level specification
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prj_impl option top "{{ top }}"
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{% endif %}
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{% if includes %}# Verilog Includes
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{% for include in includes %}
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prj_impl option -append {include path} {{ "{"+include+"}" }}
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{% endfor %}
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{% endif %}
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{% if defines %}# Verilog Defines
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{% for key, value in defines.items() %}
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prj_impl option -append VERILOG_DIRECTIVES {{ key }}={{ value }}
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{% endfor %}
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{% endif %}
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{% if params %}# Verilog Parameters / VHDL Generics
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{% for key, value in params.items() %}
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prj_impl option -append HDL_PARAM {{ key }}={{ value }}
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{% endfor %}
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{% endif %}
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{% if hooks %}{{ hooks.postcfg | join('\n') }}{% endif %}
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prj_project save
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prj_project close
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{% endif %}
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{% if 'syn' in steps or 'par' in steps or 'bit' in steps %}# Design flow -----------------------------------------------------------------
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prj_project open {{ project }}.ldf
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{% if 'syn' in steps %}# Synthesis
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{% if hooks %}{{ hooks.presyn | join('\n') }}{% endif %}
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prj_run Synthesis -forceOne
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{% if hooks %}{{ hooks.postsyn | join('\n') }}{% endif %}
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{% endif %}
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{% if 'par' in steps %} # Translate, Map, and Place and Route
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{% if hooks %}{{ hooks.prepar | join('\n') }}{% endif %}
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prj_run Translate -forceOne
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prj_run Map -forceOne
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prj_run PAR -forceOne
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{% if hooks %}{{ hooks.postpar | join('\n') }}{% endif %}
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{% endif %}
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{% if 'bit' in steps %}# Bitstream generation
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{% if hooks %}{{ hooks.prebit | join('\n') }}{% endif %}
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prj_run Export -task Bitgen -forceOne
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{% if hooks %}{{ hooks.postbit | join('\n') }}{% endif %}
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{% endif %}
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prj_project save
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prj_project close
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{% endif %}

‎tests/mocks/diamondc‎

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#!/usr/bin/env python3
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#
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# Copyright (C) 2024 PyFPGA Project
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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import argparse
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import subprocess
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import sys
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parser = argparse.ArgumentParser()
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parser.add_argument('source')
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args = parser.parse_args()
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tool = parser.prog
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tcl = f'''
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proc unknown args {{ }}
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source {args.source}
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'''
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with open(f'{tool}-mock.tcl', 'w', encoding='utf-8') as file:
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file.write(tcl)
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subprocess.run(
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f'tclsh {tool}-mock.tcl',
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shell=True,
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check=True,
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universal_newlines=True
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)
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print(f'INFO:the {tool.upper()} mock has been executed')

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