Commit c5081f6
authored
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
3 | 3 | | |
4 | 4 | | |
5 | 5 | | |
6 | | - | |
7 | | - | |
| 6 | + | |
| 7 | + | |
8 | 8 | | |
9 | 9 | | |
10 | 10 | | |
| |||
- .github/workflows/main.yml-41
- .github/workflows/nightly.yml+40-1
- Makefile+15-4
- README.md+1-1
- build.sc+1-1
- emu.mk+82
- gsim.mk+10-14
- scripts/coverage/coverage.py+3-3
- scripts/coverage/statistics.py+72-72
- src/main/scala/common/Mem.scala+223-247
- src/test/csrc/common/ram.cpp+36
- src/test/csrc/common/ram.h+2
- src/test/csrc/emu/emu.cpp+8-17
- src/test/csrc/emu/emu.h+1
- src/test/csrc/emu/main.cpp+1-7
- src/test/csrc/emu/simulator.h
- src/test/csrc/fpga/fpga_main.cpp+9
- src/test/csrc/fpga/xdma.h+7
- src/test/csrc/gsim/gsim.cpp
- src/test/csrc/gsim/gsim.h
- src/test/csrc/plugin/simfrontend/ftq.cpp+36-21
- src/test/csrc/plugin/simfrontend/ftq.h+16-2
- src/test/csrc/plugin/simfrontend/simfrontend.cpp+13-10
- src/test/csrc/plugin/simfrontend/simfrontend.h+1-1
- src/test/csrc/vcs/vcs_main.cpp+9
- src/test/csrc/verilator/simulator.cpp-22
- src/test/csrc/verilator/snapshot.cpp+1-1
- src/test/csrc/verilator/verilator.cpp-3
- src/test/csrc/verilator/waveform.cpp+1-1
- src/test/vsrc/common/ram.v+20
- src/test/vsrc/vcs/DifftestEndpoint.sv+7
- vcs.mk+1-1
- verilator.mk+64-87
0 commit comments