diff --git a/hdl/fpga/platforms/bladerf-micro/vhdl/rx-adsb.vhd b/hdl/fpga/platforms/bladerf-micro/vhdl/rx-adsb.vhd
index 9dc1f3e1b..f5dee323a 100644
--- a/hdl/fpga/platforms/bladerf-micro/vhdl/rx-adsb.vhd
+++ b/hdl/fpga/platforms/bladerf-micro/vhdl/rx-adsb.vhd
@@ -48,6 +48,9 @@ entity rx is
         trigger_master         : in    std_logic;
         trigger_line           : inout std_logic; -- this is not good, should be in/out/oe
 
+        -- 8-bit mode
+        eight_bit_mode_en      : in std_logic := '0';
+
         -- Packet to host via FX3
         packet_en              : in    std_logic;
         packet_control         : in    packet_control_t;
@@ -250,6 +253,8 @@ begin
             packet_control      =>  packet_control,
             packet_ready        =>  packet_ready,
 
+            eight_bit_mode_en   => eight_bit_mode_en,
+
             meta_fifo_full      =>  meta_fifo.wfull,
             meta_fifo_usedw     =>  meta_fifo.wused,
             meta_fifo_data      =>  meta_fifo.wdata,
@@ -266,7 +271,7 @@ begin
 
     loopback_fifo_control : process( rx_reset, loopback_fifo.rclock )
         variable offset     : natural range 0 to loopback_fifo.rdata'length;
-        variable remaining  : natural range 0 to loopback_fifo.rdata'length/32;
+        variable remaining  : natural range 0 to loopback_fifo.rdata'length/16;
         variable loopdata   : std_logic_vector(loopback_fifo.rdata'range);
     begin
         if( rx_reset = '1' ) then
@@ -295,7 +300,11 @@ begin
                 -- We have fresh data!
                 loopback_fifo.rreq <= '0';
                 loopdata    := loopback_fifo.rdata;
-                remaining   := loopback_fifo.rdata'length/32;
+                if( eight_bit_mode_en = '0' ) then
+                    remaining := loopback_fifo.rdata'length/32;
+                else
+                    remaining := loopback_fifo.rdata'length/16;
+                end if;
             elsif( remaining = 0 and sample_fifo.wfull = '0' and loopback_fifo.rempty = '0' ) then
                 -- Read more from the FIFO if we can
                 loopback_fifo.rreq <= '1';
@@ -304,16 +313,30 @@ begin
             -- Do the loopback
             for i in loopback_streams'range loop
 
-                offset := loopdata'length - (remaining*32);
+                if( eight_bit_mode_en = '0' ) then
+                    offset := loopdata'length - (remaining*32);
+                else
+                    offset := loopdata'length - (remaining*16);
+                end if;
 
                 if( adc_controls(i).enable = '1' and remaining > 0 ) then
-                    loopback_streams(i).data_i <=
-                        resize(signed(loopdata(offset+11 downto offset+0)),
-                                loopback_streams(i).data_i'length);
+                    if( eight_bit_mode_en = '0' ) then
+                        loopback_streams(i).data_i <=
+                            resize(signed(loopdata(offset+11 downto offset+0)),
+                                    loopback_streams(i).data_i'length);
+
+                        loopback_streams(i).data_q <=
+                            resize(signed(loopdata(offset+27 downto offset+16)),
+                                    loopback_streams(i).data_q'length);
+                    else
+                        loopback_streams(i).data_i <=
+                            shift_left(resize(signed(loopdata(offset+7 downto offset+0)),
+                                    loopback_streams(i).data_i'length), 4);
 
-                    loopback_streams(i).data_q <=
-                        resize(signed(loopdata(offset+27 downto offset+16)),
-                                loopback_streams(i).data_q'length);
+                        loopback_streams(i).data_q <=
+                            shift_left(resize(signed(loopdata(offset+15 downto offset+8)),
+                                    loopback_streams(i).data_q'length), 4);
+                    end if;
 
                     loopback_streams(i).data_v <= '1';
 
@@ -334,6 +357,7 @@ begin
             enable          =>  rx_enable,
 
             mode            =>  rx_gen_mode,
+            eightbit_en     => eight_bit_mode_en,
 
             sample_i        =>  rx_gen_i,
             sample_q        =>  rx_gen_q,