docs(dn): Ghala Buarish 09/28/25 (#397)

* update design notebook

* update design notebook

* update notebook

* updated notebook

* updated here

* merged old

* design notebook

* updated notebook

* Resolve gb2789.md — keep ours (empty commit if nothing staged)

* update

---------

Co-authored-by: Noahms12 <[email protected]>

Author: Ghqlq

src/design_notebooks/2025fall/gb2789.md

@@ -2,21 +2,30 @@ Ghala's Design Notebook: Processor Design VIP
 -
 ### Week1: 09/08/25 - 09/14/25
 ---
-### 09/08/25 - 09/14/25
+## Week1: 09/08/25 - 09/14/25
 - Attended the first meeting of the semester.
 - Created this notebook.
 - Read "Design Notebooks and Git" and "Development Environment".
 - Completed necessary downloads (Homebrew,CMake, Verilator). Didn't download VirtualBox because it says in the guide I don't need it if I have a macOS.
 - Downloaded VSCode and suggested add-ons.
 - Made a profile in HDLBits and completed “Getting Started” and “Verilog Language Basics”.
 
-### Week2: 09/15/25 - 09/21/25
+## Week2: 09/15/25 - 09/21/25
 - Met with partner [Lucy Zheng](https://github.com/Tyjihn) to work on the RiSC-16 module Program Counter.
 - Solved the Vectors practice on HDLBits. 
 
 [RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects)
 
 My partner and I had different approach to write the PC module but very similar logic. However I am not sure how correct it is since there is no way to test it. We faced some difficulty with figuring out the logic of the module because it is unclear what are the given inputs and which operations should the PC do or not do.
 
+## Week3: 09/22/25 - 09/28/25
+- Matched my program counter code to the testbench provided to us.
+- Created the ALU for the RiSC-16 processor. 
+  
+**Changes done to pc:** 
+1. I had the opCode as an input, now I'm using MUX_output which decides which operation for the pc to do in upstream logic. That made it simpler because I removed opcode decoding inside PC.
+2. Removed RegB port and old beq equality logic, now I'm using alu_out directly.
+3. sign-extension of imm so it can be summed with pc.
+4. reset is now active-low to match the testbench.
 
-
+**Discuss ALU:** My implementation of the ALU is similar to the implementation uploaded by Noah. However, I used mux using the conditional operator instead of an always block. I'm not familiar with how to use the always block for mux and the differences.