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src/design_notebooks/2025fall/cac10141.md
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+Weeks 1-6:
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+- Set up development environment
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+- Refamiliarized myself with verilog
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+- Worked with team (Louai and Aaquil) on weekly assignments
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+- Primarily spent my own time working on the ALU while meeting up with team to discuss other assignments
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+- Began work on data memory test bench and tasked with working on control module
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