diff --git a/.gitmodules b/.gitmodules index 6f62952f435..4f229afbe12 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,67 +1,70 @@ [submodule "3rdparty/blobs"] path = 3rdparty/blobs - url = ../blobs.git + url = https://github.com/MrChromebox/blobs.git update = none ignore = dirty [submodule "util/nvidia-cbootimage"] path = util/nvidia/cbootimage - url = ../nvidia-cbootimage.git + url = https://review.coreboot.org/nvidia-cbootimage.git [submodule "vboot"] path = 3rdparty/vboot - url = ../vboot.git + url = https://review.coreboot.org/vboot.git branch = main [submodule "arm-trusted-firmware"] path = 3rdparty/arm-trusted-firmware - url = ../arm-trusted-firmware.git + url = https://review.coreboot.org/arm-trusted-firmware.git [submodule "3rdparty/chromeec"] path = 3rdparty/chromeec - url = ../chrome-ec.git + url = https://review.coreboot.org/chrome-ec.git [submodule "libhwbase"] path = 3rdparty/libhwbase - url = ../libhwbase.git + url = https://review.coreboot.org/libhwbase.git [submodule "libgfxinit"] path = 3rdparty/libgfxinit - url = ../libgfxinit.git + url = https://review.coreboot.org/libgfxinit.git [submodule "3rdparty/fsp"] path = 3rdparty/fsp - url = ../fsp.git + url = https://review.coreboot.org/fsp.git update = none ignore = dirty [submodule "opensbi"] path = 3rdparty/opensbi - url = ../opensbi.git + url = https://review.coreboot.org/opensbi.git [submodule "intel-microcode"] path = 3rdparty/intel-microcode - url = ../intel-microcode.git + url = https://review.coreboot.org/intel-microcode.git update = none ignore = dirty branch = main [submodule "3rdparty/ffs"] path = 3rdparty/ffs - url = ../ffs.git + url = https://review.coreboot.org/ffs.git [submodule "3rdparty/amd_blobs"] path = 3rdparty/amd_blobs - url = ../amd_blobs + url = https://review.coreboot.org/amd_blobs update = none ignore = dirty [submodule "3rdparty/cmocka"] path = 3rdparty/cmocka - url = ../cmocka.git + url = https://review.coreboot.org/cmocka.git update = none branch = stable-1.1 [submodule "3rdparty/qc_blobs"] path = 3rdparty/qc_blobs - url = ../qc_blobs.git + url = https://review.coreboot.org/qc_blobs.git update = none ignore = dirty [submodule "3rdparty/intel-sec-tools"] path = 3rdparty/intel-sec-tools - url = ../9esec-security-tooling.git + url = https://review.coreboot.org/9esec-security-tooling.git [submodule "3rdparty/stm"] path = 3rdparty/stm - url = ../STM + url = https://review.coreboot.org/STM branch = stmpe [submodule "util/goswid"] path = util/goswid - url = ../goswid + url = https://review.coreboot.org/goswid branch = trunk +[submodule "3rdparty/purism-blobs"] + path = 3rdparty/purism-blobs + url = https://source.puri.sm/coreboot/purism-blobs.git diff --git a/3rdparty/blobs b/3rdparty/blobs index 01ba15667f3..0b5d0e63178 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 01ba15667f34793580f5edd0de1e26b7a542cac6 +Subproject commit 0b5d0e63178d6a5a05d13a85b28a6f4d7ccf7c2b diff --git a/3rdparty/purism-blobs b/3rdparty/purism-blobs new file mode 160000 index 00000000000..51227164fe6 --- /dev/null +++ b/3rdparty/purism-blobs @@ -0,0 +1 @@ +Subproject commit 51227164fe693042b66c7372f54057d8082dff08 diff --git a/build-uefi.sh b/build-uefi.sh new file mode 100755 index 00000000000..0c40bf33eb3 --- /dev/null +++ b/build-uefi.sh @@ -0,0 +1,47 @@ +#!/usr/bin/env bash +# + +set -e + +platforms=('snb_ivb' 'hsw' 'byt' 'bdw' 'bsw' 'skl' 'apl' 'kbl' 'whl' 'glk' \ + 'cml' 'jsl' 'tgl' 'str' 'zen2' 'adl') +build_targets=() + +json_file=cbmodels.json +rom_path=https://www.mrchromebox.tech/files/firmware/full_rom/ +echo -e "{" > $json_file + +if [ -z "$1" ]; then + for subdir in "${platforms[@]}"; do + for cfg in configs/$subdir/config*.*; do + build_targets+=("$(basename $cfg | cut -f2 -d'.')") + done + done +else + build_targets=($@) +fi + +# get git rev +rev=$(git describe --tags --dirty) + +for device in "${build_targets[@]}"; do + filename="coreboot_tiano-${device}-mrchromebox_$(date +"%Y%m%d").rom" + rm -f ~/dev/firmware/${filename}* + rm -rf ./build + cfg_file=$(find ./configs -name "config.$device.uefi") + cp "$cfg_file" .config + echo "CONFIG_LOCALVERSION=\"${rev}\"" >> .config + make clean + make olddefconfig + make -j$(nproc) + cp ./build/coreboot.rom ./${filename} + sha1sum ${filename} > ${filename}.sha1 + echo -e "\t\"${device}\": {" >> $json_file + echo -e "\t\t\"url\": \"${rom_path}${filename}\"," >> $json_file + echo -e "\t\t\"sha1\": \"$(cat ${filename}.sha1 | awk 'NR==1{print $1}')\"" >> $json_file + echo -e "\t}," >> $json_file + mv ${filename}* ~/dev/firmware/ +done +echo -e "}" >> $json_file +# remove last comma +sed -i 's/\(.*\),/\1/' $json_file diff --git a/cbfs/bootorder.emmc b/cbfs/bootorder.emmc new file mode 100644 index 00000000000..280d61c2a4b --- /dev/null +++ b/cbfs/bootorder.emmc @@ -0,0 +1,7 @@ +/rom@etc/sdcard0 +/rom@etc/sdcard1 +/rom@etc/sdcard2 +/rom@etc/sdcard3 +/rom@etc/sdcard4 +/rom@etc/sdcard5 +/rom@etc/sdcard6 diff --git a/cbfs/bootorder.emmc.apl b/cbfs/bootorder.emmc.apl new file mode 100644 index 00000000000..da6673c3d22 --- /dev/null +++ b/cbfs/bootorder.emmc.apl @@ -0,0 +1 @@ +/pci@i0cf8/*@1c diff --git a/cbfs/bootorder.ssd b/cbfs/bootorder.ssd new file mode 100644 index 00000000000..095fb7237c7 --- /dev/null +++ b/cbfs/bootorder.ssd @@ -0,0 +1 @@ +/pci@i0cf8/*@1f,2/drive@0/disk@0 diff --git a/cbfs/bootorder.usb b/cbfs/bootorder.usb new file mode 100644 index 00000000000..c666c6876a3 --- /dev/null +++ b/cbfs/bootorder.usb @@ -0,0 +1,48 @@ +/pci@i0cf8/usb@14/usb-*@0 +/pci@i0cf8/usb@14/usb-*@1 +/pci@i0cf8/usb@14/usb-*@2 +/pci@i0cf8/usb@14/usb-*@3 +/pci@i0cf8/usb@14/usb-*@4 +/pci@i0cf8/usb@14/usb-*@5 +/pci@i0cf8/usb@14/usb-*@6 +/pci@i0cf8/usb@14/usb-*@7 +/pci@i0cf8/usb@14/usb-*@8 +/pci@i0cf8/usb@14/usb-*@9 +/pci@i0cf8/usb@14/usb-*@a +/pci@i0cf8/usb@14/usb-*@b +/pci@i0cf8/usb@14/usb-*@c +/pci@i0cf8/usb@14/usb-*@d +/pci@i0cf8/usb@14/usb-*@e +/pci@i0cf8/usb@14/usb-*@f +/pci@i0cf8/usb@14/hub@1/usb-*@0 +/pci@i0cf8/usb@14/hub@1/usb-*@1 +/pci@i0cf8/usb@14/hub@1/usb-*@2 +/pci@i0cf8/usb@14/hub@1/usb-*@3 +/pci@i0cf8/usb@14/hub@1/usb-*@4 +/pci@i0cf8/usb@14/hub@1/usb-*@5 +/pci@i0cf8/usb@14/hub@1/usb-*@6 +/pci@i0cf8/usb@14/hub@1/usb-*@7 +/pci@i0cf8/usb@14/hub@1/usb-*@8 +/pci@i0cf8/usb@14/hub@1/usb-*@9 +/pci@i0cf8/usb@14/hub@1/usb-*@a +/pci@i0cf8/usb@14/hub@1/usb-*@b +/pci@i0cf8/usb@14/hub@1/usb-*@c +/pci@i0cf8/usb@14/hub@1/usb-*@d +/pci@i0cf8/usb@14/hub@1/usb-*@e +/pci@i0cf8/usb@14/hub@1/usb-*@f +/pci@i0cf8/usb@1d/hub@1/*@0 +/pci@i0cf8/usb@1d/hub@1/*@1 +/pci@i0cf8/usb@1d/hub@1/*@2 +/pci@i0cf8/usb@1d/hub@1/*@3 +/pci@i0cf8/usb@1d/hub@1/*@4 +/pci@i0cf8/usb@1d/hub@1/*@5 +/pci@i0cf8/usb@1d/hub@1/*@6 +/pci@i0cf8/usb@1d/hub@1/*@7 +/pci@i0cf8/usb@1d/hub@1/usb-*@0 +/pci@i0cf8/usb@1d/hub@1/usb-*@1 +/pci@i0cf8/usb@1d/hub@1/usb-*@2 +/pci@i0cf8/usb@1d/hub@1/usb-*@3 +/pci@i0cf8/usb@1d/hub@1/usb-*@4 +/pci@i0cf8/usb@1d/hub@1/usb-*@5 +/pci@i0cf8/usb@1d/hub@1/usb-*@6 +/pci@i0cf8/usb@1d/hub@1/usb-*@7 diff --git a/cbfs/links.apl b/cbfs/links.apl new file mode 100644 index 00000000000..804f02f14bb --- /dev/null +++ b/cbfs/links.apl @@ -0,0 +1,2 @@ +pci8086,5a84.rom seavgabios.rom +pci8086,5a85.rom seavgabios.rom diff --git a/cbfs/links.bsw b/cbfs/links.bsw new file mode 100644 index 00000000000..234cef3f194 --- /dev/null +++ b/cbfs/links.bsw @@ -0,0 +1,2 @@ +pci8086,22b0.rom pci8086,22b0.rom +pci8086,22b1.rom pci8086,22b0.rom diff --git a/cbfs/links.hswbdw b/cbfs/links.hswbdw new file mode 100644 index 00000000000..4242209ee61 --- /dev/null +++ b/cbfs/links.hswbdw @@ -0,0 +1,6 @@ +pci8086,0a06.rom pci8086,0406.rom # HSW U GT1 +pci8086,0a16.rom pci8086,0406.rom # HSW U GT2 +pci8086,0a26.rom pci8086,0406.rom # HSW U GT3 +pci8086,1606.rom pci8086,0406.rom # BDW U GT1 +pci8086,1616.rom pci8086,0406.rom # BDW U GT2 +pci8086,1626.rom pci8086,0406.rom # BDW U GT3 diff --git a/cbfs/links.kbl b/cbfs/links.kbl new file mode 100644 index 00000000000..0ba983308e3 --- /dev/null +++ b/cbfs/links.kbl @@ -0,0 +1,5 @@ +pci8086,5906.rom seavgabios.rom # Kabylake GT1 SULTM +pci8086,591e.rom seavgabios.rom # Kabylake GT2 SULXM +pci8086,5916.rom seavgabios.rom # Kabylake GT2 SULTM +pci8086,5917.rom seavgabios.rom # Kabylake GT2 SULTMR +pci8086,591b.rom seavgabios.rom # Kabylake GT2 SHALM diff --git a/cbfs/links.sbib b/cbfs/links.sbib new file mode 100644 index 00000000000..66a59191c60 --- /dev/null +++ b/cbfs/links.sbib @@ -0,0 +1,10 @@ +pci8086,0106.rom pci8086,0106.rom +pci8086,0116.rom pci8086,0106.rom +pci8086,0126.rom pci8086,0106.rom +pci8086,0136.rom pci8086,0106.rom +pci8086,0146.rom pci8086,0106.rom +pci8086,0156.rom pci8086,0106.rom +pci8086,0166.rom pci8086,0106.rom +pci8086,0176.rom pci8086,0106.rom +pci8086,0186.rom pci8086,0106.rom +pci8086,0196.rom pci8086,0106.rom diff --git a/cbfs/links.skl b/cbfs/links.skl new file mode 100644 index 00000000000..2f903d66bac --- /dev/null +++ b/cbfs/links.skl @@ -0,0 +1,3 @@ +pci8086,1906.rom pci8086,0406.rom # SKL GT1 ULT +pci8086,1916.rom pci8086,0406.rom # SKL GT2 ULT +pci8086,191e.rom pci8086,0406.rom # SKL GT2 ULX diff --git a/configs/adl/config.banshee.uefi b/configs/adl/config.banshee.uefi new file mode 100644 index 00000000000..ae247cee7d6 --- /dev/null +++ b/configs/adl/config.banshee.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x400000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/brya/banshee/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/brya/banshee/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/brya/banshee/me.bin" +CONFIG_BOARD_GOOGLE_BANSHEE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/brya/banshee/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/brya/banshee/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +# CONFIG_SMMSTORE is not set diff --git a/configs/apl/config.astronaut.uefi b/configs/apl/config.astronaut.uefi new file mode 100644 index 00000000000..0672c1fb29a --- /dev/null +++ b/configs/apl/config.astronaut.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Astronaut" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.babymega.uefi b/configs/apl/config.babymega.uefi new file mode 100644 index 00000000000..9c1f7b6bf60 --- /dev/null +++ b/configs/apl/config.babymega.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Babymega" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.babytiger.uefi b/configs/apl/config.babytiger.uefi new file mode 100644 index 00000000000..50801afbc74 --- /dev/null +++ b/configs/apl/config.babytiger.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Babytiger" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.blacktip.uefi b/configs/apl/config.blacktip.uefi new file mode 100644 index 00000000000..a31988b5615 --- /dev/null +++ b/configs/apl/config.blacktip.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blacktip" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.blue.uefi b/configs/apl/config.blue.uefi new file mode 100644 index 00000000000..de5ebf5d894 --- /dev/null +++ b/configs/apl/config.blue.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blue" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.bruce.uefi b/configs/apl/config.bruce.uefi new file mode 100644 index 00000000000..d39b87895f1 --- /dev/null +++ b/configs/apl/config.bruce.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Bruce" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.coral.uefi b/configs/apl/config.coral.uefi new file mode 100644 index 00000000000..f711df82aa6 --- /dev/null +++ b/configs/apl/config.coral.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.electro.uefi b/configs/apl/config.electro.uefi new file mode 100644 index 00000000000..0cb045f1ea3 --- /dev/null +++ b/configs/apl/config.electro.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_REEF=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Electro" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/reef/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/reef/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.epaulette.uefi b/configs/apl/config.epaulette.uefi new file mode 100644 index 00000000000..b085420287b --- /dev/null +++ b/configs/apl/config.epaulette.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Epaulette" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.lava.uefi b/configs/apl/config.lava.uefi new file mode 100644 index 00000000000..6297c9a2e9c --- /dev/null +++ b/configs/apl/config.lava.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Lava" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.nasher.uefi b/configs/apl/config.nasher.uefi new file mode 100644 index 00000000000..7d0c7b35bda --- /dev/null +++ b/configs/apl/config.nasher.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Nasher" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.nasher360.uefi b/configs/apl/config.nasher360.uefi new file mode 100644 index 00000000000..35e988621eb --- /dev/null +++ b/configs/apl/config.nasher360.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Nasher360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.pyro.uefi b/configs/apl/config.pyro.uefi new file mode 100644 index 00000000000..d1dfc859532 --- /dev/null +++ b/configs/apl/config.pyro.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PYRO=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/pyro/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/pyro/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.rabbid.uefi b/configs/apl/config.rabbid.uefi new file mode 100644 index 00000000000..8383c6eb712 --- /dev/null +++ b/configs/apl/config.rabbid.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Rabbid" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.reef.uefi b/configs/apl/config.reef.uefi new file mode 100644 index 00000000000..9fbb8832006 --- /dev/null +++ b/configs/apl/config.reef.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_REEF=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/reef/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/reef/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.robo.uefi b/configs/apl/config.robo.uefi new file mode 100644 index 00000000000..7f5f208cd4f --- /dev/null +++ b/configs/apl/config.robo.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Robo" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.robo360.uefi b/configs/apl/config.robo360.uefi new file mode 100644 index 00000000000..fa654b03322 --- /dev/null +++ b/configs/apl/config.robo360.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Robo360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.sand.uefi b/configs/apl/config.sand.uefi new file mode 100644 index 00000000000..1d9a1f107e5 --- /dev/null +++ b/configs/apl/config.sand.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_SAND=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/sand/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/sand/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.santa.uefi b/configs/apl/config.santa.uefi new file mode 100644 index 00000000000..5500e69e74c --- /dev/null +++ b/configs/apl/config.santa.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Santa" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.snappy.uefi b/configs/apl/config.snappy.uefi new file mode 100644 index 00000000000..387ceaf3d57 --- /dev/null +++ b/configs/apl/config.snappy.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_SNAPPY=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/snappy/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/snappy/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/apl/config.whitetip.uefi b/configs/apl/config.whitetip.uefi new file mode 100644 index 00000000000..1b658b93473 --- /dev/null +++ b/configs/apl/config.whitetip.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Whitetip" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/bdw/config.auron_paine.uefi b/configs/bdw/config.auron_paine.uefi new file mode 100644 index 00000000000..4ad58dbd05f --- /dev/null +++ b/configs/bdw/config.auron_paine.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_AURON_PAINE=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/paine/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bdw/config.auron_yuna.uefi b/configs/bdw/config.auron_yuna.uefi new file mode 100644 index 00000000000..23e01848df8 --- /dev/null +++ b/configs/bdw/config.auron_yuna.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_AURON_YUNA=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/yuna/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bdw/config.buddy.uefi b/configs/bdw/config.buddy.uefi new file mode 100644 index 00000000000..f40846f7e26 --- /dev/null +++ b/configs/bdw/config.buddy.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/auron/buddy/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_BUDDY=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/buddy/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bdw/config.gandof.uefi b/configs/bdw/config.gandof.uefi new file mode 100644 index 00000000000..a048d0d70ac --- /dev/null +++ b/configs/bdw/config.gandof.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_GANDOF=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/gandof/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bdw/config.guado.uefi b/configs/bdw/config.guado.uefi new file mode 100644 index 00000000000..63a48566433 --- /dev/null +++ b/configs/bdw/config.guado.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/me.bin" +CONFIG_BOARD_GOOGLE_GUADO=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/box/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/box/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bdw/config.librem_13v1.uefi b/configs/bdw/config.librem_13v1.uefi new file mode 100644 index 00000000000..ef3544fd612 --- /dev/null +++ b/configs/bdw/config.librem_13v1.uefi @@ -0,0 +1,13 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0x5C0000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_bdw/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_bdw/me.bin" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/purism-blobs/mainboard/purism/librem_bdw/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/purism-blobs/mainboard/purism/librem_bdw/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y diff --git a/configs/bdw/config.librem_15v2.uefi b/configs/bdw/config.librem_15v2.uefi new file mode 100644 index 00000000000..9750cb30abf --- /dev/null +++ b/configs/bdw/config.librem_15v2.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0x5C0000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_bdw/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_bdw/me.bin" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_BOARD_PURISM_LIBREM15_V2=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/purism-blobs/mainboard/purism/librem_bdw/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/purism-blobs/mainboard/purism/librem_bdw/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y diff --git a/configs/bdw/config.lulu.uefi b/configs/bdw/config.lulu.uefi new file mode 100644 index 00000000000..0fd0e80529c --- /dev/null +++ b/configs/bdw/config.lulu.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_LULU=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/lulu/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bdw/config.rikku.uefi b/configs/bdw/config.rikku.uefi new file mode 100644 index 00000000000..316dfeb45de --- /dev/null +++ b/configs/bdw/config.rikku.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/me.bin" +CONFIG_BOARD_GOOGLE_RIKKU=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/box/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/box/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bdw/config.samus.uefi b/configs/bdw/config.samus.uefi new file mode 100644 index 00000000000..3840aaa69ab --- /dev/null +++ b/configs/bdw/config.samus.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1275 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/auron/samus/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/auron/samus/me.bin" +CONFIG_BOARD_GOOGLE_SAMUS=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/samus/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/bdw/config.tidus.uefi b/configs/bdw/config.tidus.uefi new file mode 100644 index 00000000000..1986b0a78ce --- /dev/null +++ b/configs/bdw/config.tidus.uefi @@ -0,0 +1,20 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/me.bin" +CONFIG_BOARD_GOOGLE_TIDUS=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/box/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/box/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.banon.uefi b/configs/bsw/config.banon.uefi new file mode 100644 index 00000000000..532afddcd66 --- /dev/null +++ b/configs/bsw/config.banon.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/banon/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_BANON=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/banon/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/banon/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.celes.uefi b/configs/bsw/config.celes.uefi new file mode 100644 index 00000000000..d13466016c4 --- /dev/null +++ b/configs/bsw/config.celes.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/celes/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_CELES=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/celes/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/celes/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.cyan.uefi b/configs/bsw/config.cyan.uefi new file mode 100644 index 00000000000..f7f9e816832 --- /dev/null +++ b/configs/bsw/config.cyan.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/cyan/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_CYAN=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/cyan/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/cyan/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.edgar.uefi b/configs/bsw/config.edgar.uefi new file mode 100644 index 00000000000..824eb0b41e6 --- /dev/null +++ b/configs/bsw/config.edgar.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/edgar/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_EDGAR=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/edgar/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/edgar/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.kefka.uefi b/configs/bsw/config.kefka.uefi new file mode 100644 index 00000000000..83edce1c643 --- /dev/null +++ b/configs/bsw/config.kefka.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/kefka/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_KEFKA=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/kefka/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/kefka/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.reks.uefi b/configs/bsw/config.reks.uefi new file mode 100644 index 00000000000..ee9c4fb3e8d --- /dev/null +++ b/configs/bsw/config.reks.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/reks/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_REKS=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/reks/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/reks/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.relm.uefi b/configs/bsw/config.relm.uefi new file mode 100644 index 00000000000..16d8a31076d --- /dev/null +++ b/configs/bsw/config.relm.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/relm/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_RELM=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/relm/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/relm/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.setzer.uefi b/configs/bsw/config.setzer.uefi new file mode 100644 index 00000000000..574dd7bbf82 --- /dev/null +++ b/configs/bsw/config.setzer.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/setzer/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_SETZER=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/setzer/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/setzer/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.terra.uefi b/configs/bsw/config.terra.uefi new file mode 100644 index 00000000000..f5c819ae0be --- /dev/null +++ b/configs/bsw/config.terra.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/terra/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_TERRA=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/terra/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/terra/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.ultima.uefi b/configs/bsw/config.ultima.uefi new file mode 100644 index 00000000000..6247acc4eea --- /dev/null +++ b/configs/bsw/config.ultima.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/ultima/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_ULTIMA=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/ultima/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/ultima/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/bsw/config.wizpig.uefi b/configs/bsw/config.wizpig.uefi new file mode 100644 index 00000000000..096c7d0df41 --- /dev/null +++ b/configs/bsw/config.wizpig.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/wizpig/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_WIZPIG=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/wizpig/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/wizpig/fsp.bin" +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.banjo.uefi b/configs/byt/config.banjo.uefi new file mode 100644 index 00000000000..78716cca712 --- /dev/null +++ b/configs/byt/config.banjo.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_BANJO=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/banjo/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.candy.uefi b/configs/byt/config.candy.uefi new file mode 100644 index 00000000000..0ac4999c608 --- /dev/null +++ b/configs/byt/config.candy.uefi @@ -0,0 +1,21 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_VGA_BIOS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_CANDY=y +CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/google/rambi/candy/vgabios.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/candy/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_INTEL_GMA_ADD_VBT is not set diff --git a/configs/byt/config.clapper.uefi b/configs/byt/config.clapper.uefi new file mode 100644 index 00000000000..be217f1dafe --- /dev/null +++ b/configs/byt/config.clapper.uefi @@ -0,0 +1,21 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_VGA_BIOS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_CLAPPER=y +CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/google/rambi/clapper/vgabios.bin" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_S3_VGA_ROM_RUN is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/clapper/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_INTEL_GMA_ADD_VBT is not set diff --git a/configs/byt/config.enguarde.uefi b/configs/byt/config.enguarde.uefi new file mode 100644 index 00000000000..61b53aa416e --- /dev/null +++ b/configs/byt/config.enguarde.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_ENGUARDE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/enguarde/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.glimmer.uefi b/configs/byt/config.glimmer.uefi new file mode 100644 index 00000000000..a7454bc8824 --- /dev/null +++ b/configs/byt/config.glimmer.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_GLIMMER=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/glimmer/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.gnawty.uefi b/configs/byt/config.gnawty.uefi new file mode 100644 index 00000000000..e776162a862 --- /dev/null +++ b/configs/byt/config.gnawty.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_GNAWTY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/gnawty/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.heli.uefi b/configs/byt/config.heli.uefi new file mode 100644 index 00000000000..ddc95117d12 --- /dev/null +++ b/configs/byt/config.heli.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_HELI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/heli/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.kip.uefi b/configs/byt/config.kip.uefi new file mode 100644 index 00000000000..fa62bd76735 --- /dev/null +++ b/configs/byt/config.kip.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_KIP=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/kip/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.ninja.uefi b/configs/byt/config.ninja.uefi new file mode 100644 index 00000000000..e1376613836 --- /dev/null +++ b/configs/byt/config.ninja.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_NINJA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/ninja/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.orco.uefi b/configs/byt/config.orco.uefi new file mode 100644 index 00000000000..defe086105d --- /dev/null +++ b/configs/byt/config.orco.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_ORCO=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/orco/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.quawks.uefi b/configs/byt/config.quawks.uefi new file mode 100644 index 00000000000..427b2fbf24e --- /dev/null +++ b/configs/byt/config.quawks.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_QUAWKS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/quawks/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.squawks.uefi b/configs/byt/config.squawks.uefi new file mode 100644 index 00000000000..4927d2642b5 --- /dev/null +++ b/configs/byt/config.squawks.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_SQUAWKS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/squawks/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.sumo.uefi b/configs/byt/config.sumo.uefi new file mode 100644 index 00000000000..0a5a357f518 --- /dev/null +++ b/configs/byt/config.sumo.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_SUMO=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/sumo/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.swanky.uefi b/configs/byt/config.swanky.uefi new file mode 100644 index 00000000000..f6ba0ef2b70 --- /dev/null +++ b/configs/byt/config.swanky.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_SWANKY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/swanky/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/byt/config.winky.uefi b/configs/byt/config.winky.uefi new file mode 100644 index 00000000000..9b88d996a6b --- /dev/null +++ b/configs/byt/config.winky.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_WINKY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/winky/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.akemi.uefi b/configs/cml/config.akemi.uefi new file mode 100644 index 00000000000..531f9cf5eea --- /dev/null +++ b/configs/cml/config.akemi.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/akemi/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/akemi/me.bin" +CONFIG_BOARD_GOOGLE_AKEMI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/akemi/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/cml/config.dooly.uefi b/configs/cml/config.dooly.uefi new file mode 100644 index 00000000000..35ac9914d17 --- /dev/null +++ b/configs/cml/config.dooly.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dooly/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff_legacy/me.bin" +CONFIG_BOARD_GOOGLE_DOOLY=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.dragonair.uefi b/configs/cml/config.dragonair.uefi new file mode 100644 index 00000000000..811bdfed0f6 --- /dev/null +++ b/configs/cml/config.dragonair.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dratini/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dratini/me.bin" +CONFIG_BOARD_GOOGLE_DRATINI=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Dragonair" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/dratini/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.drallion.uefi b/configs/cml/config.drallion.uefi new file mode 100644 index 00000000000..58153f57f18 --- /dev/null +++ b/configs/cml/config.drallion.uefi @@ -0,0 +1,17 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/drallion/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/drallion/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/drallion/me.bin" +CONFIG_BOARD_GOOGLE_DRALLION=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/drallion/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_EC_BIN=y +CONFIG_EC_BIN_PATH="3rdparty/blobs/mainboard/google/drallion/ec.bin" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x1028 +CONFIG_DRIVERS_PS2_KEYBOARD=y diff --git a/configs/cml/config.dratini.uefi b/configs/cml/config.dratini.uefi new file mode 100644 index 00000000000..c50113555ed --- /dev/null +++ b/configs/cml/config.dratini.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dratini/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dratini/me.bin" +CONFIG_BOARD_GOOGLE_DRATINI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/dratini/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.duffy.uefi b/configs/cml/config.duffy.uefi new file mode 100644 index 00000000000..03abc059d4d --- /dev/null +++ b/configs/cml/config.duffy.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_DUFFY=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.faffy.uefi b/configs/cml/config.faffy.uefi new file mode 100644 index 00000000000..9cc028a4929 --- /dev/null +++ b/configs/cml/config.faffy.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_FAFFY=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.helios.uefi b/configs/cml/config.helios.uefi new file mode 100644 index 00000000000..168a75218ec --- /dev/null +++ b/configs/cml/config.helios.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/helios/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/helios/me.bin" +CONFIG_BOARD_GOOGLE_HELIOS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/helios/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.jinlon.uefi b/configs/cml/config.jinlon.uefi new file mode 100644 index 00000000000..c095f5a6fc2 --- /dev/null +++ b/configs/cml/config.jinlon.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/jinlon/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/jinlon/me.bin" +CONFIG_BOARD_GOOGLE_JINLON=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/jinlon/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.kaisa.uefi b/configs/cml/config.kaisa.uefi new file mode 100644 index 00000000000..4c83f7daa57 --- /dev/null +++ b/configs/cml/config.kaisa.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_KAISA=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.kindred.uefi b/configs/cml/config.kindred.uefi new file mode 100644 index 00000000000..3e3a5fd02b0 --- /dev/null +++ b/configs/cml/config.kindred.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kindred/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kindred/me.bin" +CONFIG_BOARD_GOOGLE_KINDRED=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/kindred/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.kled.uefi b/configs/cml/config.kled.uefi new file mode 100644 index 00000000000..5c899cc4e83 --- /dev/null +++ b/configs/cml/config.kled.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kindred/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kindred/me.bin" +CONFIG_BOARD_GOOGLE_KINDRED=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Kled" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/kindred/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.kohaku.uefi b/configs/cml/config.kohaku.uefi new file mode 100644 index 00000000000..da1804b5a9a --- /dev/null +++ b/configs/cml/config.kohaku.uefi @@ -0,0 +1,13 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kohaku/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kohaku/me.bin" +CONFIG_BOARD_GOOGLE_KOHAKU=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/kohaku/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y diff --git a/configs/cml/config.librem_14.uefi b/configs/cml/config.librem_14.uefi new file mode 100644 index 00000000000..65ecef59ada --- /dev/null +++ b/configs/cml/config.librem_14.uefi @@ -0,0 +1,11 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0x900000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/librem_14/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/librem_14/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM_14=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_cnl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.librem_mini_v2.uefi b/configs/cml/config.librem_mini_v2.uefi new file mode 100644 index 00000000000..772a95fa1db --- /dev/null +++ b/configs/cml/config.librem_mini_v2.uefi @@ -0,0 +1,11 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0xA00000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/mini_v2/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/mini_v2/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM_MINI_V2=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_cnl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.nightfury.uefi b/configs/cml/config.nightfury.uefi new file mode 100644 index 00000000000..8e2086eb5c3 --- /dev/null +++ b/configs/cml/config.nightfury.uefi @@ -0,0 +1,13 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/nightfury/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/nightfury/me.bin" +CONFIG_BOARD_GOOGLE_NIGHTFURY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/nightfury/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y diff --git a/configs/cml/config.noibat.uefi b/configs/cml/config.noibat.uefi new file mode 100644 index 00000000000..541cbf1f635 --- /dev/null +++ b/configs/cml/config.noibat.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/noibat/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_NOIBAT=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/cml/config.wyvern.uefi b/configs/cml/config.wyvern.uefi new file mode 100644 index 00000000000..a1991f77456 --- /dev/null +++ b/configs/cml/config.wyvern.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/wyvern/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_WYVERN=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/glk/config.ampton.uefi b/configs/glk/config.ampton.uefi new file mode 100644 index 00000000000..06719fe7530 --- /dev/null +++ b/configs/glk/config.ampton.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/ampton/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_AMPTON=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/ampton/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/ampton/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.apel.uefi b/configs/glk/config.apel.uefi new file mode 100644 index 00000000000..fc2dc8a2fb3 --- /dev/null +++ b/configs/glk/config.apel.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/ampton/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_AMPTON=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Apel" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/ampton/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/ampton/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.bloog.uefi b/configs/glk/config.bloog.uefi new file mode 100644 index 00000000000..5b55eaf36b6 --- /dev/null +++ b/configs/glk/config.bloog.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bloog/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BLOOG=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bloog/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bloog/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.blooglet.uefi b/configs/glk/config.blooglet.uefi new file mode 100644 index 00000000000..01fe30795f9 --- /dev/null +++ b/configs/glk/config.blooglet.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bloog/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BLOOG=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blooglet" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bloog/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bloog/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.blooguard.uefi b/configs/glk/config.blooguard.uefi new file mode 100644 index 00000000000..16ff3d59c7d --- /dev/null +++ b/configs/glk/config.blooguard.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bloog/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BLOOG=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blooguard" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bloog/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bloog/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.blorb.uefi b/configs/glk/config.blorb.uefi new file mode 100644 index 00000000000..9bee6ee3da1 --- /dev/null +++ b/configs/glk/config.blorb.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blorb" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.bluebird.uefi b/configs/glk/config.bluebird.uefi new file mode 100644 index 00000000000..41cd6ff0ddf --- /dev/null +++ b/configs/glk/config.bluebird.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/casta/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CASTA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Bluebird" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/casta/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/casta/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/casta/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.bobba.uefi b/configs/glk/config.bobba.uefi new file mode 100644 index 00000000000..e41c2942977 --- /dev/null +++ b/configs/glk/config.bobba.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.bobba360.uefi b/configs/glk/config.bobba360.uefi new file mode 100644 index 00000000000..7fa8edfac9a --- /dev/null +++ b/configs/glk/config.bobba360.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Bobba360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.casta.uefi b/configs/glk/config.casta.uefi new file mode 100644 index 00000000000..ba5d18db5e7 --- /dev/null +++ b/configs/glk/config.casta.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/casta/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CASTA=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/casta/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/casta/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/casta/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.dood.uefi b/configs/glk/config.dood.uefi new file mode 100644 index 00000000000..99345e15944 --- /dev/null +++ b/configs/glk/config.dood.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/dood/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_DOOD=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/dood/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/dood/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/dood/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.dorp.uefi b/configs/glk/config.dorp.uefi new file mode 100644 index 00000000000..e192c1e0cc8 --- /dev/null +++ b/configs/glk/config.dorp.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/meep/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Dorp" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/meep/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/meep/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.droid.uefi b/configs/glk/config.droid.uefi new file mode 100644 index 00000000000..d2d586e47f6 --- /dev/null +++ b/configs/glk/config.droid.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Droid" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.fleex.uefi b/configs/glk/config.fleex.uefi new file mode 100644 index 00000000000..33bc56bfedc --- /dev/null +++ b/configs/glk/config.fleex.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/fleex/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FLEEX=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/fleex/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/fleex/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.foob.uefi b/configs/glk/config.foob.uefi new file mode 100644 index 00000000000..304f5412595 --- /dev/null +++ b/configs/glk/config.foob.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/foob/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FOOB=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/foob/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/foob/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/foob/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.foob360.uefi b/configs/glk/config.foob360.uefi new file mode 100644 index 00000000000..7d50260b5c9 --- /dev/null +++ b/configs/glk/config.foob360.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/foob/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FOOB=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Foob360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/foob/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/foob/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/foob/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.garfour.uefi b/configs/glk/config.garfour.uefi new file mode 100644 index 00000000000..7b762e0f5a3 --- /dev/null +++ b/configs/glk/config.garfour.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/garg/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_GARG=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Garfour" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/garg/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/garg/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/garg/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.garg.uefi b/configs/glk/config.garg.uefi new file mode 100644 index 00000000000..703e75a300d --- /dev/null +++ b/configs/glk/config.garg.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/garg/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_GARG=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/garg/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/garg/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/garg/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.garg360.uefi b/configs/glk/config.garg360.uefi new file mode 100644 index 00000000000..c695dbb03de --- /dev/null +++ b/configs/glk/config.garg360.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/garg/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_GARG=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Garg360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/garg/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/garg/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/garg/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.grabbiter.uefi b/configs/glk/config.grabbiter.uefi new file mode 100644 index 00000000000..e3c3a743899 --- /dev/null +++ b/configs/glk/config.grabbiter.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/fleex/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FLEEX=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Grabbiter" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/fleex/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/fleex/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.laser.uefi b/configs/glk/config.laser.uefi new file mode 100644 index 00000000000..c22c40a8444 --- /dev/null +++ b/configs/glk/config.laser.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Laser" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.laser14.uefi b/configs/glk/config.laser14.uefi new file mode 100644 index 00000000000..0cfeab1f7cf --- /dev/null +++ b/configs/glk/config.laser14.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Laser14" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.lick.uefi b/configs/glk/config.lick.uefi new file mode 100644 index 00000000000..5330bfcbba7 --- /dev/null +++ b/configs/glk/config.lick.uefi @@ -0,0 +1,13 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/lick/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_LICK=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/lick/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/lick/cpu_microcode_blob.bin" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.meep.uefi b/configs/glk/config.meep.uefi new file mode 100644 index 00000000000..765ebeac30b --- /dev/null +++ b/configs/glk/config.meep.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/meep/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/meep/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/meep/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.mimrock.uefi b/configs/glk/config.mimrock.uefi new file mode 100644 index 00000000000..363ea102920 --- /dev/null +++ b/configs/glk/config.mimrock.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/mimrock/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Mimrock" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/mimrock/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/mimrock/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.nospike.uefi b/configs/glk/config.nospike.uefi new file mode 100644 index 00000000000..ac6f5ce5eb5 --- /dev/null +++ b/configs/glk/config.nospike.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/ampton/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_AMPTON=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Nospike" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/ampton/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/ampton/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.orbatrix.uefi b/configs/glk/config.orbatrix.uefi new file mode 100644 index 00000000000..e49d37e6291 --- /dev/null +++ b/configs/glk/config.orbatrix.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/fleex/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FLEEX=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Orbatrix" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/fleex/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/fleex/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.phaser.uefi b/configs/glk/config.phaser.uefi new file mode 100644 index 00000000000..b882912df60 --- /dev/null +++ b/configs/glk/config.phaser.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.phaser360.uefi b/configs/glk/config.phaser360.uefi new file mode 100644 index 00000000000..9de95bbf6f3 --- /dev/null +++ b/configs/glk/config.phaser360.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Phaser360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.phaser360s.uefi b/configs/glk/config.phaser360s.uefi new file mode 100644 index 00000000000..561b545c189 --- /dev/null +++ b/configs/glk/config.phaser360s.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Phaser360s" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.sparky.uefi b/configs/glk/config.sparky.uefi new file mode 100644 index 00000000000..3cfb8de3010 --- /dev/null +++ b/configs/glk/config.sparky.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Sparky" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.sparky360.uefi b/configs/glk/config.sparky360.uefi new file mode 100644 index 00000000000..5f8a82eddfc --- /dev/null +++ b/configs/glk/config.sparky360.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Sparky360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.vorticon.uefi b/configs/glk/config.vorticon.uefi new file mode 100644 index 00000000000..45dd9f96b1b --- /dev/null +++ b/configs/glk/config.vorticon.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/meep/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Vorticon" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/meep/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/meep/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/glk/config.vortininja.uefi b/configs/glk/config.vortininja.uefi new file mode 100644 index 00000000000..6b278f1d443 --- /dev/null +++ b/configs/glk/config.vortininja.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/meep/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Vortininja" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/meep/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/meep/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/hsw/config.falco.uefi b/configs/hsw/config.falco.uefi new file mode 100644 index 00000000000..d8abbd4c091 --- /dev/null +++ b/configs/hsw/config.falco.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/me.bin" +CONFIG_BOARD_GOOGLE_FALCO=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/book/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/slippy/falco/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/hsw/config.leon.uefi b/configs/hsw/config.leon.uefi new file mode 100644 index 00000000000..c44cb0ac1ae --- /dev/null +++ b/configs/hsw/config.leon.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/me.bin" +CONFIG_BOARD_GOOGLE_LEON=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/book/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/slippy/leon/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/hsw/config.mccloud.uefi b/configs/hsw/config.mccloud.uefi new file mode 100644 index 00000000000..d80e6c22c4c --- /dev/null +++ b/configs/hsw/config.mccloud.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_MCCLOUD=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/hsw/config.monroe.uefi b/configs/hsw/config.monroe.uefi new file mode 100644 index 00000000000..69f8e0d1803 --- /dev/null +++ b/configs/hsw/config.monroe.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_MONROE=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/hsw/config.panther.uefi b/configs/hsw/config.panther.uefi new file mode 100644 index 00000000000..1053404dd48 --- /dev/null +++ b/configs/hsw/config.panther.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/soc/intel/hsw/box/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_PANTHER=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/hsw/config.peppy.uefi b/configs/hsw/config.peppy.uefi new file mode 100644 index 00000000000..df5d50bb361 --- /dev/null +++ b/configs/hsw/config.peppy.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/me.bin" +CONFIG_BOARD_GOOGLE_PEPPY=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/book/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/slippy/peppy/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/hsw/config.tricky.uefi b/configs/hsw/config.tricky.uefi new file mode 100644 index 00000000000..7f43c3d6d03 --- /dev/null +++ b/configs/hsw/config.tricky.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_TRICKY=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/hsw/config.wolf.uefi b/configs/hsw/config.wolf.uefi new file mode 100644 index 00000000000..17f8202dfd6 --- /dev/null +++ b/configs/hsw/config.wolf.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/me.bin" +CONFIG_BOARD_GOOGLE_WOLF=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/book/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/slippy/wolf/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/hsw/config.zako.uefi b/configs/hsw/config.zako.uefi new file mode 100644 index 00000000000..fc5c93592dc --- /dev/null +++ b/configs/hsw/config.zako.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_ZAKO=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/jsl/config.bugzzy.uefi b/configs/jsl/config.bugzzy.uefi new file mode 100644 index 00000000000..26ccb60f34e --- /dev/null +++ b/configs/jsl/config.bugzzy.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/dedede/bugzzy/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/bugzzy/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/bugzzy/me.bin" +CONFIG_BOARD_GOOGLE_BUGZZY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/bugzzy/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/bugzzy/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/bugzzy/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/jsl/config.drawcia.uefi b/configs/jsl/config.drawcia.uefi new file mode 100644 index 00000000000..4f845c672dc --- /dev/null +++ b/configs/jsl/config.drawcia.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/me.bin" +CONFIG_BOARD_GOOGLE_DRAWCIA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/drawcia/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/jsl/config.drawlat.uefi b/configs/jsl/config.drawlat.uefi new file mode 100644 index 00000000000..e45d8146358 --- /dev/null +++ b/configs/jsl/config.drawlat.uefi @@ -0,0 +1,17 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/me.bin" +CONFIG_BOARD_GOOGLE_DRAWCIA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Drawlat" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/drawcia/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/jsl/config.drawman.uefi b/configs/jsl/config.drawman.uefi new file mode 100644 index 00000000000..1f169cafc37 --- /dev/null +++ b/configs/jsl/config.drawman.uefi @@ -0,0 +1,17 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/me.bin" +CONFIG_BOARD_GOOGLE_DRAWCIA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Drawman" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/drawcia/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/jsl/config.lantis.uefi b/configs/jsl/config.lantis.uefi new file mode 100644 index 00000000000..9e737423360 --- /dev/null +++ b/configs/jsl/config.lantis.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/dedede/lantis/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/lantis/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/lantis/me.bin" +CONFIG_BOARD_GOOGLE_LANTIS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/lantis/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/lantis/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/lantis/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/jsl/config.magpie.uefi b/configs/jsl/config.magpie.uefi new file mode 100644 index 00000000000..e6597694063 --- /dev/null +++ b/configs/jsl/config.magpie.uefi @@ -0,0 +1,17 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/magpie/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/magpie/me.bin" +CONFIG_BOARD_GOOGLE_MAGOLOR=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Magpie" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/magpie/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/magpie/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/magpie/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y diff --git a/configs/kbl/config.atlas.uefi b/configs/kbl/config.atlas.uefi new file mode 100644 index 00000000000..197e7626a27 --- /dev/null +++ b/configs/kbl/config.atlas.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1080 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/atlas/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/atlas/me.bin" +CONFIG_BOARD_GOOGLE_ATLAS=y +CONFIG_INCLUDE_NHLT_BLOBS_ATLAS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/kbl/config.eve.uefi b/configs/kbl/config.eve.uefi new file mode 100644 index 00000000000..5f79eb3daac --- /dev/null +++ b/configs/kbl/config.eve.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/eve/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/eve/me.bin" +CONFIG_BOARD_GOOGLE_EVE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/eve/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/kbl/config.fizz.uefi b/configs/kbl/config.fizz.uefi new file mode 100644 index 00000000000..de356be329b --- /dev/null +++ b/configs/kbl/config.fizz.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/fizz/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/fizz/me.bin" +CONFIG_BOARD_GOOGLE_FIZZ=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/fizz/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/kbl/config.karma.uefi b/configs/kbl/config.karma.uefi new file mode 100644 index 00000000000..80691541660 --- /dev/null +++ b/configs/kbl/config.karma.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/fizz/karma/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/fizz/karma/me.bin" +CONFIG_BOARD_GOOGLE_KARMA=y +CONFIG_EDK2_BOOT_TIMEOUT=5 +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/kbl/config.leona.uefi b/configs/kbl/config.leona.uefi new file mode 100644 index 00000000000..82383f1097c --- /dev/null +++ b/configs/kbl/config.leona.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/rammus/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/rammus/me.bin" +CONFIG_BOARD_GOOGLE_RAMMUS=y +CONFIG_INCLUDE_NHLT_BLOBS_RAMMUS=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Leona" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/kbl/config.librem_13v4.uefi b/configs/kbl/config.librem_13v4.uefi new file mode 100644 index 00000000000..c072cc254e6 --- /dev/null +++ b/configs/kbl/config.librem_13v4.uefi @@ -0,0 +1,9 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0xe00000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_kbl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_kbl/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM13_V4=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y diff --git a/configs/kbl/config.librem_15v4.uefi b/configs/kbl/config.librem_15v4.uefi new file mode 100644 index 00000000000..9d08f010207 --- /dev/null +++ b/configs/kbl/config.librem_15v4.uefi @@ -0,0 +1,11 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0xe00000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1080 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_kbl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_kbl/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM15_V4=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y diff --git a/configs/kbl/config.nami.uefi b/configs/kbl/config.nami.uefi new file mode 100644 index 00000000000..53c2d3eb907 --- /dev/null +++ b/configs/kbl/config.nami.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nami/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nami/me.bin" +CONFIG_BOARD_GOOGLE_NAMI=y +CONFIG_OEM_BIN_FILE="3rdparty/blobs/mainboard/google/poppy/nami/oem.bin" +CONFIG_INCLUDE_NHLT_BLOBS_NAMI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/kbl/config.nautilus.uefi b/configs/kbl/config.nautilus.uefi new file mode 100644 index 00000000000..aac2ce19bee --- /dev/null +++ b/configs/kbl/config.nautilus.uefi @@ -0,0 +1,13 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nautilus/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nautilus/me.bin" +CONFIG_BOARD_GOOGLE_NAUTILUS=y +CONFIG_INCLUDE_NHLT_BLOBS_NAUTILUS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/kbl/config.nocturne.uefi b/configs/kbl/config.nocturne.uefi new file mode 100644 index 00000000000..0aef0c74cfe --- /dev/null +++ b/configs/kbl/config.nocturne.uefi @@ -0,0 +1,13 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nocturne/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nocturne/me.bin" +CONFIG_BOARD_GOOGLE_NOCTURNE=y +CONFIG_INCLUDE_NHLT_BLOBS_NOCTURNE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/kbl/config.shyvana.uefi b/configs/kbl/config.shyvana.uefi new file mode 100644 index 00000000000..22a558976bb --- /dev/null +++ b/configs/kbl/config.shyvana.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/rammus/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/rammus/me.bin" +CONFIG_BOARD_GOOGLE_RAMMUS=y +CONFIG_INCLUDE_NHLT_BLOBS_RAMMUS=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Shyvana" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_POST_IO_PORT=0x80 diff --git a/configs/kbl/config.soraka.uefi b/configs/kbl/config.soraka.uefi new file mode 100644 index 00000000000..dae779a70f1 --- /dev/null +++ b/configs/kbl/config.soraka.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/soraka/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/soraka/me.bin" +CONFIG_BOARD_GOOGLE_SORAKA=y +CONFIG_OEM_BIN_FILE="3rdparty/blobs/mainboard/google/poppy/soraka/oem.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/skl/config.asuka.uefi b/configs/skl/config.asuka.uefi new file mode 100644 index 00000000000..f36c00c997b --- /dev/null +++ b/configs/skl/config.asuka.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/asuka/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/asuka/me.bin" +CONFIG_BOARD_GOOGLE_ASUKA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/asuka/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/skl/config.caroline.uefi b/configs/skl/config.caroline.uefi new file mode 100644 index 00000000000..a6276572e40 --- /dev/null +++ b/configs/skl/config.caroline.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1200 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1800 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/caroline/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/caroline/me.bin" +CONFIG_BOARD_GOOGLE_CAROLINE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/caroline/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/skl/config.cave.uefi b/configs/skl/config.cave.uefi new file mode 100644 index 00000000000..f6d8d9a1d4f --- /dev/null +++ b/configs/skl/config.cave.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/cave/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/cave/me.bin" +CONFIG_BOARD_GOOGLE_CAVE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/cave/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/skl/config.chell.uefi b/configs/skl/config.chell.uefi new file mode 100644 index 00000000000..355b024af64 --- /dev/null +++ b/configs/skl/config.chell.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1080 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/chell/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/chell/me.bin" +CONFIG_BOARD_GOOGLE_CHELL=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/chell/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/skl/config.lars.uefi b/configs/skl/config.lars.uefi new file mode 100644 index 00000000000..927c9681b5c --- /dev/null +++ b/configs/skl/config.lars.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/lars/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/lars/me.bin" +CONFIG_BOARD_GOOGLE_LARS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/lars/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/skl/config.librem_13v2.uefi b/configs/skl/config.librem_13v2.uefi new file mode 100644 index 00000000000..f841c9639f9 --- /dev/null +++ b/configs/skl/config.librem_13v2.uefi @@ -0,0 +1,9 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0xe00000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_skl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_skl/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM13_V2=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_skl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y diff --git a/configs/skl/config.librem_15v3.uefi b/configs/skl/config.librem_15v3.uefi new file mode 100644 index 00000000000..e3a8c71056c --- /dev/null +++ b/configs/skl/config.librem_15v3.uefi @@ -0,0 +1,9 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0xe00000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_skl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_skl/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM15_V3=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_skl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y diff --git a/configs/skl/config.sentry.uefi b/configs/skl/config.sentry.uefi new file mode 100644 index 00000000000..2d83876aaba --- /dev/null +++ b/configs/skl/config.sentry.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/sentry/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/sentry/me.bin" +CONFIG_BOARD_GOOGLE_SENTRY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/sentry/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/snb_ivb/config.butterfly.uefi b/configs/snb_ivb/config.butterfly.uefi new file mode 100644 index 00000000000..8e6fe25fae1 --- /dev/null +++ b/configs/snb_ivb/config.butterfly.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="Google" +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/butterfly/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/butterfly/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/butterfly/me.bin" +CONFIG_BOARD_GOOGLE_BUTTERFLY=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/snb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y diff --git a/configs/snb_ivb/config.link.uefi b/configs/snb_ivb/config.link.uefi new file mode 100644 index 00000000000..5c910f46e7e --- /dev/null +++ b/configs/snb_ivb/config.link.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1275 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/link/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/link/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/link/me.bin" +CONFIG_BOARD_GOOGLE_LINK=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/ivb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/link/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_GOP_DRIVER_VERSION="3.0.1030" diff --git a/configs/snb_ivb/config.lumpy.uefi b/configs/snb_ivb/config.lumpy.uefi new file mode 100644 index 00000000000..73edc664c41 --- /dev/null +++ b/configs/snb_ivb/config.lumpy.uefi @@ -0,0 +1,13 @@ +CONFIG_VENDOR_SAMSUNG=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/samsung/lumpy/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/samsung/lumpy/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/samsung/lumpy/me.bin" +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/snb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y diff --git a/configs/snb_ivb/config.parrot.uefi b/configs/snb_ivb/config.parrot.uefi new file mode 100644 index 00000000000..82c49fb0c12 --- /dev/null +++ b/configs/snb_ivb/config.parrot.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/parrot/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/parrot/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/parrot/me.bin" +CONFIG_BOARD_GOOGLE_PARROT=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/ivb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y diff --git a/configs/snb_ivb/config.stout.uefi b/configs/snb_ivb/config.stout.uefi new file mode 100644 index 00000000000..ef087233b87 --- /dev/null +++ b/configs/snb_ivb/config.stout.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/stout/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/stout/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/stout/me.bin" +CONFIG_BOARD_GOOGLE_STOUT=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/ivb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y diff --git a/configs/snb_ivb/config.stumpy.uefi b/configs/snb_ivb/config.stumpy.uefi new file mode 100644 index 00000000000..c3092f647b7 --- /dev/null +++ b/configs/snb_ivb/config.stumpy.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_SAMSUNG=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GOOGLE" +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/samsung/stumpy/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/samsung/stumpy/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/samsung/stumpy/me.bin" +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_BOARD_SAMSUNG_STUMPY=y +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/snb/cpu_microcode_blob.bin" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y diff --git a/configs/snb_ivb/config.x230.uefi b/configs/snb_ivb/config.x230.uefi new file mode 100644 index 00000000000..287e84598e4 --- /dev/null +++ b/configs/snb_ivb/config.x230.uefi @@ -0,0 +1,9 @@ +CONFIG_VENDOR_LENOVO=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x400000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_LENOVO_X230=y +CONFIG_H8_SUPPORT_BT_ON_WIFI=y +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_VPD is not set diff --git a/configs/str/config.aleena.uefi b/configs/str/config.aleena.uefi new file mode 100644 index 00000000000..ae07bb8e278 --- /dev/null +++ b/configs/str/config.aleena.uefi @@ -0,0 +1,11 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_ALEENA=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/aleena/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 diff --git a/configs/str/config.barla.uefi b/configs/str/config.barla.uefi new file mode 100644 index 00000000000..eae7924bd42 --- /dev/null +++ b/configs/str/config.barla.uefi @@ -0,0 +1,12 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_CAREENA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Barla" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/careena/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 diff --git a/configs/str/config.careena.uefi b/configs/str/config.careena.uefi new file mode 100644 index 00000000000..a9e1cc58a95 --- /dev/null +++ b/configs/str/config.careena.uefi @@ -0,0 +1,11 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_CAREENA=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/careena/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 diff --git a/configs/str/config.kasumi.uefi b/configs/str/config.kasumi.uefi new file mode 100644 index 00000000000..ec4943faa61 --- /dev/null +++ b/configs/str/config.kasumi.uefi @@ -0,0 +1,12 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_ALEENA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Kasumi" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/aleena/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 diff --git a/configs/str/config.liara.uefi b/configs/str/config.liara.uefi new file mode 100644 index 00000000000..984aa56993c --- /dev/null +++ b/configs/str/config.liara.uefi @@ -0,0 +1,11 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_LIARA=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/liara/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 diff --git a/configs/str/config.treeya.uefi b/configs/str/config.treeya.uefi new file mode 100644 index 00000000000..ee4635e1495 --- /dev/null +++ b/configs/str/config.treeya.uefi @@ -0,0 +1,11 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_TREEYA=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/treeya/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 diff --git a/configs/tgl/config.chronicler.uefi b/configs/tgl/config.chronicler.uefi new file mode 100644 index 00000000000..bd80bef3d21 --- /dev/null +++ b/configs/tgl/config.chronicler.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/chronicler/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/chronicler/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/chronicler/me.bin" +CONFIG_BOARD_GOOGLE_CHRONICLER=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/chronicler/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/chronicler/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/tgl/config.collis.uefi b/configs/tgl/config.collis.uefi new file mode 100644 index 00000000000..4e468a78316 --- /dev/null +++ b/configs/tgl/config.collis.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/collis/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/collis/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/collis/me.bin" +CONFIG_BOARD_GOOGLE_COLLIS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/collis/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/collis/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/tgl/config.copano.uefi b/configs/tgl/config.copano.uefi new file mode 100644 index 00000000000..fa6619e6136 --- /dev/null +++ b/configs/tgl/config.copano.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/copano/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/copano/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/copano/me.bin" +CONFIG_BOARD_GOOGLE_COPANO=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/copano/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/copano/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/tgl/config.delbin.uefi b/configs/tgl/config.delbin.uefi new file mode 100644 index 00000000000..0520a68ddff --- /dev/null +++ b/configs/tgl/config.delbin.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/delbin/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/delbin/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/delbin/me.bin" +CONFIG_BOARD_GOOGLE_DELBIN=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/delbin/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/delbin/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/tgl/config.drobit.uefi b/configs/tgl/config.drobit.uefi new file mode 100644 index 00000000000..077ef47f10c --- /dev/null +++ b/configs/tgl/config.drobit.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/drobit/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/drobit/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/drobit/me.bin" +CONFIG_BOARD_GOOGLE_DROBIT=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/drobit/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/drobit/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/tgl/config.eldrid.uefi b/configs/tgl/config.eldrid.uefi new file mode 100644 index 00000000000..35f31f09e1e --- /dev/null +++ b/configs/tgl/config.eldrid.uefi @@ -0,0 +1,17 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/eldrid/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/eldrid/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/eldrid/me.bin" +CONFIG_BOARD_GOOGLE_ELDRID=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/eldrid/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/eldrid/ec.RW.flat" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=n +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/tgl/config.elemi.uefi b/configs/tgl/config.elemi.uefi new file mode 100644 index 00000000000..de9c3a257d0 --- /dev/null +++ b/configs/tgl/config.elemi.uefi @@ -0,0 +1,16 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/elemi/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/elemi/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/elemi/me.bin" +CONFIG_BOARD_GOOGLE_ELEMI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/elemi/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/elemi/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/tgl/config.lillipup.uefi b/configs/tgl/config.lillipup.uefi new file mode 100644 index 00000000000..77851c1b775 --- /dev/null +++ b/configs/tgl/config.lillipup.uefi @@ -0,0 +1,15 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/lillipup/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/lillipup/me.bin" +CONFIG_BOARD_GOOGLE_LINDAR=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Lillipup" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/lillipup/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/lillipup/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/tgl/config.lindar.uefi b/configs/tgl/config.lindar.uefi new file mode 100644 index 00000000000..399514aae8d --- /dev/null +++ b/configs/tgl/config.lindar.uefi @@ -0,0 +1,14 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/lindar/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/lindar/me.bin" +CONFIG_BOARD_GOOGLE_LINDAR=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/lindar/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/lindar/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y diff --git a/configs/tgl/config.voema.uefi b/configs/tgl/config.voema.uefi new file mode 100644 index 00000000000..e71d7356308 --- /dev/null +++ b/configs/tgl/config.voema.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/voema/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/voema/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/voema/me.bin" +CONFIG_BOARD_GOOGLE_VOEMA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/voema/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/voema/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/tgl/config.volet.uefi b/configs/tgl/config.volet.uefi new file mode 100644 index 00000000000..cc9a160ae49 --- /dev/null +++ b/configs/tgl/config.volet.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/volet/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/volet/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/volet/me.bin" +CONFIG_BOARD_GOOGLE_VOLET=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/volet/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/volet/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/tgl/config.volta.uefi b/configs/tgl/config.volta.uefi new file mode 100644 index 00000000000..f68844d13ce --- /dev/null +++ b/configs/tgl/config.volta.uefi @@ -0,0 +1,19 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/voxel/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/voxel/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/voxel/me.bin" +CONFIG_BOARD_GOOGLE_VOXEL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Volta" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/voxel/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/voxel/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/tgl/config.voxel.uefi b/configs/tgl/config.voxel.uefi new file mode 100644 index 00000000000..badb959349b --- /dev/null +++ b/configs/tgl/config.voxel.uefi @@ -0,0 +1,18 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/voxel/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/voxel/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/voxel/me.bin" +CONFIG_BOARD_GOOGLE_VOXEL=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/voxel/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/voxel/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/whl/config.librem_mini.uefi b/configs/whl/config.librem_mini.uefi new file mode 100644 index 00000000000..8c64759f279 --- /dev/null +++ b/configs/whl/config.librem_mini.uefi @@ -0,0 +1,11 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0x800000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/mini/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/mini/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM_MINI=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_cnl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/whl/config.sarien.uefi b/configs/whl/config.sarien.uefi new file mode 100644 index 00000000000..450ffd957d7 --- /dev/null +++ b/configs/whl/config.sarien.uefi @@ -0,0 +1,17 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/sarien/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/sarien/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/sarien/me.bin" +CONFIG_GBE_BIN_PATH="3rdparty/blobs/mainboard/google/sarien/gbe.bin" +CONFIG_BOARD_GOOGLE_SARIEN=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/sarien/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_GBE_BIN=y +CONFIG_HAVE_EC_BIN=y +CONFIG_EC_BIN_PATH="3rdparty/blobs/mainboard/google/sarien/ec.bin" +CONFIG_NO_GFX_INIT=y +CONFIG_EDK2_GOP_DRIVER=y diff --git a/configs/zen2/config.berknip.uefi b/configs/zen2/config.berknip.uefi new file mode 100644 index 00000000000..d29ed9612e1 --- /dev/null +++ b/configs/zen2/config.berknip.uefi @@ -0,0 +1,10 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_BOARD_GOOGLE_BERKNIP=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1d4 +# CONFIG_SMMSTORE is not set diff --git a/configs/zen2/config.dirinboz.uefi b/configs/zen2/config.dirinboz.uefi new file mode 100644 index 00000000000..78c62714bc4 --- /dev/null +++ b/configs/zen2/config.dirinboz.uefi @@ -0,0 +1,10 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_BOARD_GOOGLE_DIRINBOZ=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1d4 +# CONFIG_SMMSTORE is not set diff --git a/configs/zen2/config.morphius.uefi b/configs/zen2/config.morphius.uefi new file mode 100644 index 00000000000..bc3ce08ed6f --- /dev/null +++ b/configs/zen2/config.morphius.uefi @@ -0,0 +1,10 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_BOARD_GOOGLE_MORPHIUS=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1d4 +# CONFIG_SMMSTORE is not set diff --git a/payloads/Kconfig b/payloads/Kconfig index 2a2773a2188..a1dc5961383 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -14,7 +14,7 @@ config PAYLOAD_NONE if !PAYLOAD_NONE choice prompt "Payload to add" - default PAYLOAD_SEABIOS if ARCH_X86 + default PAYLOAD_EDK2 if ARCH_X86 config PAYLOAD_ELF bool "An ELF executable payload" diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index a2d2f505e23..6a03a5100b8 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -185,6 +185,9 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \ CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \ CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \ + CONFIG_EDK2_GOP_DRIVER=$(CONFIG_EDK2_GOP_DRIVER) \ + CONFIG_EDK2_GOP_FILE=$(CONFIG_EDK2_GOP_FILE) \ + CONFIG_EDK2_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ @@ -226,6 +229,9 @@ $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG) CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \ CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \ CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \ + CONFIG_EDK2_GOP_DRIVER=$(CONFIG_EDK2_GOP_DRIVER) \ + CONFIG_EDK2_GOP_FILE=$(CONFIG_EDK2_GOP_FILE) \ + CONFIG_EDK2_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 225a42896c0..8eddaa0ab53 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -35,6 +35,14 @@ endif checkout: fetch echo " Checking out SeaBIOS revision $(TAG-y)" cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + cd $(project_dir); \ + for patch in $(CURDIR)/patches/*.patch; do \ + echo "Applying $$patch"; \ + export GIT_COMMITTER_EMAIL="`grep 'From:' $$patch | grep -Po '<\K[^>]+@[^>]+(?=>)'`"; \ + export GIT_COMMITTER_NAME="`grep 'From:' $$patch | cut -d '<' -f 1 | tail -c +7`"; \ + git am --committer-date-is-author-date --keep-cr $$patch || \ + ( echo " Error when applying patches.\n"; git am --abort; exit 1; ); \ + done; config: checkout echo " CONFIG SeaBIOS $(TAG-y)" diff --git a/payloads/external/SeaBIOS/patches/0001-Fix-Byt-CB-Bootup-on-SeaBIOS-when-using-coreboot.patch b/payloads/external/SeaBIOS/patches/0001-Fix-Byt-CB-Bootup-on-SeaBIOS-when-using-coreboot.patch new file mode 100644 index 00000000000..9fef45c092c --- /dev/null +++ b/payloads/external/SeaBIOS/patches/0001-Fix-Byt-CB-Bootup-on-SeaBIOS-when-using-coreboot.patch @@ -0,0 +1,42 @@ +From 28f11be04379080f6eb48471edf1bd03f0d139ef Mon Sep 17 00:00:00 2001 +From: Christopher Lentocha +Date: Wed, 15 Feb 2023 09:10:33 -0500 +Subject: [PATCH] Fix Byt CB Bootup on SeaBIOS when using coreboot + +This patch helps fix the internal eMMC card when booting from it with +the MrChromebox custom coreboot distro. If this patch isn't applied, +the OS cannot boot off of it, and if you boot from USB, then you will +get spamming errors in dmesg. This also doesn't show on Windows PE if +you do not apply this, and it will be very slow to boot, or to even +use. Note that this SMM variable is currently only in the MrChromebox +coreboot distro at the moment, and is used by his EDK2 distro as well. +Also the line added in this patch should not be added to CBFS +booting, so we can assume that the next payload woll do the same thing, +like if we chainload SeaBIOS to EDK2. Also this is a dirty patch and +should not be sent to mainline SeaBIOS and people hope for it to be +removed with a coreboot fix anyways, when it isn't needed in EDK2 +as well to boot or use. Tested only on GOOGLE Enguarde at the moment. +MrChromebox = Matt DeVillier +Byt = Intel Bay Trail +CB = ChromeBook (and other Chrome OS Devices like Chromebox) + +Signed-off-by: Christopher Lentocha +--- + src/boot.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/boot.c b/src/boot.c +index 1effd80..eb79601 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -871,6 +871,7 @@ call_boot_entry(struct segoff_s bootsegip, u8 bootdrv) + // Set the magic number in ax and the boot drive in dl. + br.dl = bootdrv; + br.ax = 0xaa55; ++ outb(0xcd, 0xb2); + farcall16(&br); + } + +-- +2.35.1 + diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 454aef0069b..458708e91ba 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -53,7 +53,7 @@ config EDK2_REPOSITORY config EDK2_TAG_OR_REV string "Insert a commit's SHA-1 or a branch name" - default "origin/uefipayload_202207" if EDK2_REPO_MRCHROMEBOX + default "origin/upp_202301" if EDK2_REPO_MRCHROMEBOX default "origin/master" if EDK2_REPO_OFFICIAL default "" if EDK2_REPO_CUSTOM help @@ -134,7 +134,7 @@ config EDK2_BOOTSPLASH_FILE config EDK2_BOOT_MANAGER_ESCAPE bool "Use Escape key for Boot Manager" - default n + default y help Use Escape as the hot-key to access the Boot Manager. This replaces the default key of F2. @@ -171,7 +171,7 @@ config EDK2_CPU_TIMER_LIB config EDK2_FOLLOW_BGRT_SPEC bool "Center logo 38.2% from the top of screen" - default n + default y help Follow the BGRT Specification implemented by Microsoft and the Boot Logo 38.2% will be vertically centered 38.2% from @@ -179,11 +179,11 @@ config EDK2_FOLLOW_BGRT_SPEC config EDK2_FULL_SCREEN_SETUP bool "Use the full screen for the edk2 frontpage" - default y + default n help Allow edk2 to use the full screen to display the frontpage - (aka "Boot Menu"). With this option disable, it will be - limited to 640x480. + (aka "Boot Menu"). With this option disabled, it will be + limited to ~1024x768. config EDK2_HAVE_EFI_SHELL bool "Include EFI Shell" @@ -218,9 +218,26 @@ config EDK2_SERIAL_SUPPORT Enable serial port output in edk2. Serial output limits the performance of edk2's FrontPage. +config EDK2_GOP_DRIVER + bool "Add a GOP driver to the Tianocore build" + depends on INTEL_GMA_ADD_VBT + +config EDK2_GOP_FILE + string "GOP driver file" + depends on EDK2_GOP_DRIVER + default "3rdparty/blobs/soc/intel/bdw/IntelGopDriver.efi" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "3rdparty/blobs/soc/intel/byt/IntelGopDriver.efi" if SOC_INTEL_BAYTRAIL + default "3rdparty/blobs/soc/intel/bsw/IntelGopDriver.efi" if SOC_INTEL_BRASWELL + default "3rdparty/blobs/soc/intel/kbl/IntelGopDriver.efi" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE + default "3rdparty/blobs/soc/intel/glk/IntelGopDriver.efi" if SOC_INTEL_GEMINILAKE + default "3rdparty/blobs/soc/intel/apl/IntelGopDriver.efi" if SOC_INTEL_APOLLOLAKE + default "3rdparty/blobs/soc/intel/cml/IntelGopDriver.efi" if SOC_INTEL_COMETLAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/blobs/soc/intel/tgl/IntelGopDriver.efi" if SOC_INTEL_TIGERLAKE + default "IntelGopDriver.efi" + config EDK2_CUSTOM_BUILD_PARAMS string "edk2 additional custom build parameters" - default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2 + default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2 && !SOC_AMD_PICASSO help edk2 has build options that are not modified by coreboot, and these can be found in `UefiPayloadPkg/UefiPayloadPkg.dsc`. Forks may also support diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 27ce4a9507a..be0bf7a37be 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -96,6 +96,10 @@ endif ifneq ($(CONFIG_EDK2_SD_MMC_TIMEOUT),) BUILD_STR += -D SD_MMC_TIMEOUT=$(shell echo $$(( $(CONFIG_EDK2_SD_MMC_TIMEOUT) * 1000)) ) endif +# GOP_DRIVER = FALSE +ifeq ($(CONFIG_EDK2_GOP_DRIVER), y) +BUILD_STR += -D USE_PLATFORM_GOP=TRUE +endif # # EDKII has the below PCDs that are relevant to coreboot: @@ -189,6 +193,11 @@ print: prep: $(EDK2_PATH) clean checktools logo cd $(WORKSPACE); \ + if [ -n "$(CONFIG_EDK2_GOP_DRIVER)" ]; then \ + echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \ + cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/UefiPayloadPkg/IntelGopDriver.efi; \ + cp $(top)/$(CONFIG_EDK2_VBT_FILE) $(EDK2_PATH)/UefiPayloadPkg/vbt.bin; \ + fi; \ source $(EDK2_PATH)/edksetup.sh; \ unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \ grep -q "COREBOOT" $(EDK2_PATH)/Conf/tools_def.txt; \ diff --git a/shrinkconfigs.sh b/shrinkconfigs.sh new file mode 100644 index 00000000000..bef517faee2 --- /dev/null +++ b/shrinkconfigs.sh @@ -0,0 +1,40 @@ +#!/bin/bash + +for filename in configs/*/config.*.uefi; do + [ -e "$filename" ] || continue + cp "$filename" .config + make savedefconfig + # remove a bunch of default things 'make defconfig' leaves in + sed -i '/^CONFIG_DRIVER_TPM_SPI_BUS=0x1/d' defconfig + sed -i '/^CONFIG_DRIVER_TPM_SPI_BUS=0x1/d' defconfig + sed -i '/^CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000/d' defconfig + sed -i '/^CONFIG_EDK2_BOOT_TIMEOUT=2/d' defconfig + sed -i '/^CONFIG_UART_PCI_ADDR=0x0/d' defconfig + sed -i '/^CONFIG_SUBSYSTEM_VENDOR_ID=0x0000/d' defconfig + sed -i '/^CONFIG_SUBSYSTEM_DEVICE_ID=0x0000/d' defconfig + sed -i '/^CONFIG_I2C_TRANSFER_TIMEOUT_US=500000/d' defconfig + sed -i '/^CONFIG_SMMSTORE_SIZE=0x40000/d' defconfig + sed -i '/^CONFIG_PCIEXP_HOTPLUG_BUSES=42/d' defconfig + sed -i '/^CONFIG_PCIEXP_HOTPLUG_MEM=0xc200000/d' defconfig + sed -i '/^CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x1c000000/d' defconfig + sed -i '/^CONFIG_PCIEXP_HOTPLUG_IO=0x2000/d' defconfig + sed -i '/^CONFIG_EDK2_SD_MMC_TIMEOUT=10/d' defconfig + sed -i '/^CONFIG_FSP_LOC=0xfff6e000/d' defconfig + sed -i '/^CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600/d' defconfig + sed -i '/^CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560/d' defconfig + sed -i '/^CONFIG_PCIEXP_HOTPLUG_BUSES=8/d' defconfig + sed -i '/^CONFIG_PCIEXP_HOTPLUG_MEM=0x800000/d' defconfig + sed -i '/^CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000/d' defconfig + sed -i '/^CONFIG_CBFS_MCACHE_RW_PERCENTAGE=50/d' defconfig + sed -i '/^CONFIG_VBOOT_KEYBLOCK_VERSION=1/d' defconfig + sed -i '/^CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0/d' defconfig + sed -i '/^CONFIG_AMD_FWM_POSITION_INDEX=2/d' defconfig + sed -i '/^CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144/d' defconfig + sed -i '/^CONFIG_CBFS_SIZE=0x01000000/d' defconfig + sed -i '/^CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000/d' defconfig + sed -i '/^CONFIG_BOTTOMIO_POSITION=0xD0000000/d' defconfig + sed -i '/^CONFIG_AMD_FWM_POSITION_INDEX=1/d' defconfig + sed -i '/^CONFIG_CBFS_SIZE=0x01000000/d' defconfig + + cp defconfig "$filename" +done diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 04a59b17674..6facca19a3a 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -476,7 +476,7 @@ static void acpi_ssdt_write_cbtable(void) acpigen_write_device("CTBL"); acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE); acpigen_write_name_integer("_UID", 0); - acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_write_mem32fixed(0, base, size); diff --git a/src/device/Kconfig b/src/device/Kconfig index fdedf46100d..9bec6d0a88d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -721,12 +721,12 @@ config PCIEXP_HOTPLUG_MEM config PCIEXP_HOTPLUG_PREFETCH_MEM hex "PCI Express Hotplug Prefetch Memory" - default 0x10000000 + default 0x100000000 help This is the amount of pre-fetchable memory space, in bytes, to allocate to hot-plug PCI express bridges, for use by hotplugged child devices. This size should be page-aligned. The default is - 256 MiB. + 4 GiB. config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G bool @@ -745,11 +745,11 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G config PCIEXP_HOTPLUG_IO hex "PCI Express Hotplug I/O Space" - default 0x2000 + default 0x3000 help This is the amount of I/O space to allocate to hot-plug PCI express bridges, for use by hotplugged child devices. The default - is 8 KiB. + is 12 KiB. endif # PCIEXP_HOTPLUG @@ -964,6 +964,28 @@ config INTEL_GMA_VBT_FILE help The path and filename of the VBT binary. +config SET_GOP_DRIVER_VERSION + bool "Set the GOP Driver version" + depends on INTEL_GMA_ADD_VBT + default y if INTEL_GMA_ADD_VBT + help + Inject the GOP driver version into the OpRegion ACPI table. + +config GOP_DRIVER_VERSION + string "GOP Driver version" + depends on SET_GOP_DRIVER_VERSION + default "2.0.1024" if NORTHBRIDGE_INTEL_SANDYBRIDGE + default "5.5.1034" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "7.2.1013" if SOC_INTEL_BAYTRAIL + default "8.0.1041" if SOC_INTEL_BRASWELL + default "9.0.1080" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE + default "9.0.1107" if SOC_INTEL_COMETLAKE || SOC_INTEL_WHISKEYLAKE + default "13.0.1018" if SOC_INTEL_GEMINILAKE + default "10.0.1037" if SOC_INTEL_APOLLOLAKE + default "17.0.1064" if SOC_INTEL_TIGERLAKE + help + Must be in the format X.Y.ZZZZ + config SOFTWARE_I2C bool "Enable I2C controller emulation in software" default n diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 0942d00fc1b..8e13ffc7bb8 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -11,6 +11,7 @@ struct drivers_i2c_generic_config { const char *hid; /* ACPI _HID (required) */ const char *cid; /* ACPI _CID */ + const char *sub; /* ACPI _SUB */ const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ unsigned int uid; /* ACPI _UID */ diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index d1baeb76f40..1a3ec40c7a5 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -83,6 +83,8 @@ void i2c_generic_fill_ssdt(const struct device *dev, acpigen_write_name_string("_HID", config->hid); if (config->cid) acpigen_write_name_string("_CID", config->cid); + if (config->sub) + acpigen_write_name_string("_SUB", config->sub); acpigen_write_name_integer("_UID", config->uid); if (config->desc) acpigen_write_name_string("_DDN", config->desc); diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index d9e5a14c5b2..68aea6c80cf 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -48,7 +48,7 @@ static void i2c_sx9310_fill_ssdt(const struct device *dev) acpigen_write_name_string("_HID", I2C_SX9310_ACPI_ID); acpigen_write_name_integer("_UID", config->uid); acpigen_write_name_string("_DDN", config->desc); - acpigen_write_STA(acpi_device_status(dev)); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* Resources */ acpigen_write_name("_CRS"); diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index b2086864555..ba81cfec7f4 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -67,7 +67,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring("^^XBCL"); acpigen_pop_len(); - +#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) /* Method (_BCM, 1, NotSerialized) { @@ -78,7 +78,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * acpigen_emit_namestring("^^XBCM"); acpigen_emit_byte(ARG0_OP); acpigen_pop_len(); - +#endif /* Method (_BQC, 0, NotSerialized) { diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index fe333fa6742..ed7bea6f5ca 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -350,6 +350,12 @@ enum cb_err intel_gma_init_igd_opregion(void) /* Get the opregion version information */ opregion->header.opver = opregion_get_version(); +#if CONFIG(SET_GOP_DRIVER_VERSION) + /* Inject GOP driver version */ + memcpy(opregion->header.dver, STR16(CONFIG_GOP_DRIVER_VERSION), + 2 * strlen(CONFIG_GOP_DRIVER_VERSION)); + +#endif /* Extended VBT support */ if (is_ext_vbt_required(opregion, vbt)) { /* Place extended VBT just after opregion */ @@ -371,7 +377,10 @@ enum cb_err intel_gma_init_igd_opregion(void) // TODO Initialize Mailbox 1 opregion->mailbox1.clid = 1; - // TODO Initialize Mailbox 3 + //From Intel OpRegion reference doc + opregion->header.pcon = 279; + + // Initialize Mailbox 3 opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 1dd177c2db6..69c31a69292 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -41,8 +41,7 @@ typedef struct { #define IGD_MBOX4 (1 << 3) #define IGD_MBOX5 (1 << 4) -#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ - IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_MOBILE (IGD_MBOX1| IGD_MBOX3 | IGD_MBOX4 | IGD_MBOX5) #define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) #define SBIOS_VERSION_SIZE 32 diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 5d19d695195..c5b1224bcc5 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -110,7 +110,7 @@ static enum cb_err fetch_mac_vpd_key(u8 *macstrbuf, const char *vpd_key) search_length); if (offset == search_length) { - printk(BIOS_ERR, "Could not locate '%s' in VPD\n", vpd_key); + printk(BIOS_WARNING, "Could not locate '%s' in VPD\n", vpd_key); rdev_munmap(&rdev, search_address); return CB_ERR; } @@ -379,6 +379,7 @@ static void r8168_net_fill_ssdt(const struct device *dev) if (dev->chip_ops) acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* Power Resource */ if (CONFIG(RT8168_GEN_ACPI_POWER_RESOURCE) && config->has_power_resource) { diff --git a/src/drivers/sof/Kconfig b/src/drivers/sof/Kconfig new file mode 100644 index 00000000000..3d8bdd3ec40 --- /dev/null +++ b/src/drivers/sof/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_AUDIO_SOF + bool + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/sof/Makefile.inc b/src/drivers/sof/Makefile.inc new file mode 100644 index 00000000000..6faabe4500f --- /dev/null +++ b/src/drivers/sof/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_AUDIO_SOF) += sof.c diff --git a/src/drivers/sof/chip.h b/src/drivers/sof/chip.h new file mode 100644 index 00000000000..134c0deadc8 --- /dev/null +++ b/src/drivers/sof/chip.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_AUDIO_SOF_H__ +#define __DRIVERS_AUDIO_SOF_H__ + +#include +#include + +/* Speaker topology */ +enum _spkr_tplg { + max98373 = 1, + max98360a, + max98357a, + max98390, + rt1011, + rt1015, +}; + +/* Jack topology */ +enum _jack_tplg { + cs42l42 = 1, + da7219, + nau8825, + rt5682, +}; + +/* Mic topology */ +enum _mic_tplg { + _1ch = 1, + _2ch_pdm0, + _2ch_pdm1, + _4ch, +}; + + + +struct drivers_sof_config { + unsigned int spkr_tplg; + unsigned int jack_tplg; + unsigned int mic_tplg; +}; + +#endif /* __DRIVERS_AUDIO_SOF_H__ */ diff --git a/src/drivers/sof/sof.c b/src/drivers/sof/sof.c new file mode 100644 index 00000000000..0e2bd8f4750 --- /dev/null +++ b/src/drivers/sof/sof.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "chip.h" + +static const char *get_spkr_tplg_str(unsigned int index) { + switch (index) + { + case 1: return "max98373"; + case 2: return "max98360a"; + case 3: return "max98357a"; + case 4: return "max98390"; + case 5: return "rt1011"; + case 6: return "rt1015"; + default: return "default"; + } +} + +static const char *get_jack_tplg_str(unsigned int index) { + switch (index) + { + case 1: return "cs42l42"; + case 2: return "da7219"; + case 3: return "nau8825"; + case 4: return "rt5682"; + default: return "default"; + } +} + +static const char *get_mic_tplg_str(unsigned int index) { + switch (index) + { + case 1: return "1ch"; + case 2: return "2ch-pdm0"; + case 3: return "2ch-pdm1"; + case 4: return "4ch"; + default: return "default"; + } +} + +static void sof_fill_ssdt_generator(const struct device *dev) +{ + struct drivers_sof_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd; + + if (!dev->enabled || !config || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_string(dsd, "speaker-tplg", + get_spkr_tplg_str(config->spkr_tplg)); + acpi_dp_add_string(dsd, "hp-tplg", + get_jack_tplg_str(config->jack_tplg)); + acpi_dp_add_string(dsd, "mic-tplg", + get_mic_tplg_str(config->mic_tplg)); + acpi_dp_write(dsd); + acpigen_pop_len(); /* Scope */ +} + + +static struct device_operations sof_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = sof_fill_ssdt_generator, +}; + +static void sof_enable(struct device *dev) +{ + dev->ops = &sof_ops; +} + +struct chip_operations drivers_sof_ops = { + CHIP_NAME("SOF") + .enable_dev = sof_enable +}; diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index 7d45eb6a850..1b4f7ca9943 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -2,7 +2,7 @@ config VPD bool "Support for Vital Product Data tables" - default n + default y if !DRIVERS_GENERIC_CBFS_SERIAL help Enable support for flash based vital product data. @@ -23,4 +23,4 @@ config VPD_FMAP_SIZE config SMBIOS_SERIAL_FROM_VPD bool "Load device serial from VPD" depends on VPD && GENERATE_SMBIOS_TABLES - default n + default y diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 24b878f3f24..4bd5f60c700 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -50,7 +50,7 @@ static void init_vpd_rdev(const char *fmap_name, struct region_device *rdev) int32_t size; if (fmap_locate_area_as_rdev(fmap_name, rdev)) { - printk(BIOS_ERR, "%s: No %s FMAP section.\n", __func__, + printk(BIOS_WARNING, "%s: No %s FMAP section.\n", __func__, fmap_name); goto fail; } diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 1cf88f260b6..3651217bf6a 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -22,7 +22,7 @@ endif bootblock-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c +ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c utility.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c @@ -63,7 +63,6 @@ cbfs-files-y += ecrw ecrw-file := $(obj)/mainboard/$(MAINBOARDDIR)/ecrw ecrw-name := ecrw ecrw-type := raw -ecrw-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += ecrw.hash ecrw.hash-file := $(obj)/mainboard/$(MAINBOARDDIR)/ecrw.hash ecrw.hash-name := ecrw.hash diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 53441111677..9291e7780b8 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -279,8 +279,8 @@ Device (BAT0) }) Name (BSTP, 0) - // Workaround for full battery status, disabled by default - Name (BFWK, 0) + // Workaround for full battery status, enabled by default + Name (BFWK, 1) // Method to enable full battery workaround Method (BFWE) @@ -369,8 +369,8 @@ Device (BAT1) }) Name (BSTP, 0) - // Workaround for full battery status, disabled by default - Name (BFWK, 0) + // Workaround for full battery status, enabled by default + Name (BFWK, 1) // Method to enable full battery workaround Method (BFWE) diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 5a9541349b5..c43ce45f350 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -9,27 +9,6 @@ Device (CREC) Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) #endif -#ifdef EC_ENABLE_SYNC_IRQ - Name (_CRS, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive) - { - EC_SYNC_IRQ - } - }) -#endif - -#ifdef EC_ENABLE_SYNC_IRQ_GPIO - Name (_CRS, ResourceTemplate () - { - GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, - "\\_SB.GPIO", 0x00, ResourceConsumer, ,) - { - EC_SYNC_IRQ - } - }) -#endif - #ifdef EC_ENABLE_MKBP_DEVICE Device (CKSC) { @@ -53,7 +32,7 @@ Device (CREC) #endif Method(_STA, 0) { - Return (0xB) + Return (0xF) } #if CONFIG(DRIVERS_ACPI_THERMAL_ZONE) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 2d44ae3c1b7..adac83ecd2f 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -453,7 +453,15 @@ Device (EC0) \_SB.DPTF.TPET() #endif #ifdef EC_ENABLE_TBMC_DEVICE - Notify (TBMC, 0x80) + If (LEqual(_OSI("Linux"), 1)) { + Notify (\_SB.PCI0.LPCB.EC0.CREC.TBMC, 0x80) + } else { + If (LEqual ((^TBMD), One)) { + Notify (VBTN, 0xCC) + } Else { + Notify (VBTN, 0xCD) + } + } #endif #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) If (CondRefOf (\_SB.DPTC)) { @@ -648,5 +656,6 @@ Device (EC0) #ifdef EC_ENABLE_TBMC_DEVICE #include "tbmc.asl" + #include "vbtn.asl" #endif } diff --git a/src/ec/google/chromeec/acpi/keyboard_backlight.asl b/src/ec/google/chromeec/acpi/keyboard_backlight.asl index 87be075db08..ec8fe2636ba 100644 --- a/src/ec/google/chromeec/acpi/keyboard_backlight.asl +++ b/src/ec/google/chromeec/acpi/keyboard_backlight.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Scope (\_SB) +/* Scope modified for coolstar's Windows driver */ +Scope (\_SB.PCI0.LPCB.EC0.CREC) { /* * Chrome EC Keyboard Backlight interface @@ -10,28 +11,32 @@ Scope (\_SB) Name (_HID, "GOOG0002") Name (_UID, 1) - /* Ask EC if we even have a backlight - * Return 0xf (present, enabled, show in UI, functioning) or 0 - * - * With older EC codebases that don't support the Device - * Features bitfield, this reports the keyboard backlight as - * enabled since reads to undefined addresses in EC address - * space return 0xff and so KBLE will be 1. - */ Method (_STA, 0, NotSerialized) { - /* If query is unsupported, but this code is compiled - * in, assume the backlight exists physically. + /* If this code is compiled in, assume the backlight + * exists physically. */ - If (\_SB.PCI0.LPCB.EC0.DFUD == 1) { - Return (0xf) - } - /* If EC reports that backlight exists, trust it */ - If (\_SB.PCI0.LPCB.EC0.KBLE == 1) { - Return (0xf) - } - /* Otherwise: no device -> disable */ - Return (0) + Return (0xf) + } + } +} + +Scope (\_SB) +{ + /* + * Stub for linux driver which hardcodes location + */ + Device (KBLT) + { + Name (_HID, "GOOG0002") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) + { + Return (0x0) } /* Read current backlight value */ diff --git a/src/ec/google/chromeec/acpi/pd.asl b/src/ec/google/chromeec/acpi/pd.asl index 5b45ab1b2b9..4011643935d 100644 --- a/src/ec/google/chromeec/acpi/pd.asl +++ b/src/ec/google/chromeec/acpi/pd.asl @@ -7,6 +7,6 @@ Device (ECPD) Name (_DDN, "EC PD Device") Method(_STA, 0) { - Return (0xB) + Return (0xF) } } diff --git a/src/ec/google/chromeec/acpi/tbmc.asl b/src/ec/google/chromeec/acpi/tbmc.asl index 1661296da61..b71548625ad 100644 --- a/src/ec/google/chromeec/acpi/tbmc.asl +++ b/src/ec/google/chromeec/acpi/tbmc.asl @@ -1,20 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device (TBMC) +Scope (\_SB.PCI0.LPCB.EC0.CREC) { - Name (_HID, "GOOG0006") - Name (_UID, 1) - Name (_DDN, "Tablet Motion Control") - Method (TBMC) + Device (TBMC) { - If (^^RCTM == 1) { - Return (0x1) - } Else { - Return (0x0) + Name (_HID, "GOOG0006") + Name (_UID, 1) + Name (_DDN, "Tablet Motion Control") + Method (TBMC) + { + If (^^^RCTM == 1) { + Return (0x1) + } Else { + Return (0x0) + } + } + Method(_STA, 0) + { + Return (0xF) } - } - Method(_STA, 0) - { - Return (0xB) } } diff --git a/src/ec/google/chromeec/acpi/vbtn.asl b/src/ec/google/chromeec/acpi/vbtn.asl new file mode 100644 index 00000000000..b77d2db361d --- /dev/null +++ b/src/ec/google/chromeec/acpi/vbtn.asl @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* VGBS reports 0x40 when NOT in tablet mode. */ +/* Sent event 0xCC for tablet mode, 0xCD for laptop */ +/* Linux driver expects SMBIOS_ENCLOSURE_TYPE=SMBIOS_ENCLOSURE_CONVERTIBLE */ + +Device (VBTN) +{ + Name (_HID, "INT33D6") + Name (_DDN, "Tablet Virtual Buttons") + + Method (VBDL, 0) + { + } + + Method (VGBS) + { + If (LEqual (^^RCTM, One)) { + Return (0x0) + } Else { + Return (0x40) + } + } + Method(_STA, 0) + { + Return (0xF) + } +} + +Device (VBTO) +{ + Name (_HID, "INT33D3") + Name (_CID, "PNP0C60") + Method (_STA, 0) + { + Return (0xF) + } +} diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 646dd29848f..f75f2c0ae9f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -2,18 +2,25 @@ #include #include +#include #include +#include +#include #include #include #include #include #include +#include +#include #include #include #include #include #include "ec.h" +#include "ec_commands.h" +#include "utility.h" #define INVALID_HCMD 0xFF @@ -1339,43 +1346,78 @@ static void google_chromeec_log_uptimeinfo(void) printk(BIOS_DEBUG, "\n"); } -/* Cache and retrieve the EC image type (ro or rw) */ -enum ec_image google_chromeec_get_current_image(void) +static enum ec_current_image google_chromeec_get_version(void) { - static enum ec_image ec_image_type = EC_IMAGE_UNKNOWN; + struct chromeec_command cec_cmd; + struct ec_response_get_version cec_resp; + cec_cmd.cmd_code = EC_CMD_GET_VERSION; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = 0; + cec_cmd.cmd_data_out = &cec_resp; + cec_cmd.cmd_size_in = 0; + cec_cmd.cmd_size_out = sizeof(cec_resp); + cec_cmd.cmd_dev_index = 0; + google_chromeec_command(&cec_cmd); - if (ec_image_type != EC_IMAGE_UNKNOWN) - return ec_image_type; - - struct ec_response_get_version resp = {}; - struct chromeec_command cmd = { - .cmd_code = EC_CMD_GET_VERSION, - .cmd_version = 0, - .cmd_data_out = &resp, - .cmd_size_in = 0, - .cmd_size_out = sizeof(resp), - .cmd_dev_index = 0, - }; - int rv; - - rv = google_chromeec_command(&cmd); - - if (rv != 0) { + if (cec_cmd.cmd_code) { printk(BIOS_DEBUG, "Google Chrome EC: version command failed!\n"); + return EC_IMAGE_UNKNOWN; } else { printk(BIOS_DEBUG, "Google Chrome EC: version:\n"); - printk(BIOS_DEBUG, " ro: %s\n", resp.version_string_ro); - printk(BIOS_DEBUG, " rw: %s\n", resp.version_string_rw); + printk(BIOS_DEBUG, " ro: %s\n", cec_resp.version_string_ro); + printk(BIOS_DEBUG, " rw: %s\n", cec_resp.version_string_rw); printk(BIOS_DEBUG, " running image: %d\n", - resp.current_image); - ec_image_type = resp.current_image; + cec_resp.current_image); + return cec_resp.current_image; } +} + +/* Cached EC image type (ro or rw). */ +enum ec_current_image google_chromeec_get_current_image(void) +{ + static enum ec_current_image ec_image_type = EC_IMAGE_UNKNOWN; + + if (ec_image_type == EC_IMAGE_UNKNOWN) + ec_image_type = google_chromeec_get_version(); - /* Will still be UNKNOWN if command failed */ return ec_image_type; } +void google_chromeec_init(void) +{ + printk(BIOS_DEBUG, "Google Chrome EC: Initializing\n"); + + google_chromeec_log_uptimeinfo(); + + /* Check which EC image is active */ + google_chromeec_get_current_image(); + + /* Check/update EC RW image if needed */ + if (google_chromeec_swsync() != 0) { + printk(BIOS_ERR, "ChromeEC: EC SW SYNC FAILED\n"); + } else if (google_chromeec_get_current_image() != EC_IMAGE_RW) { + /* EC RW image is up to date, switch to it if not already*/ + google_chromeec_reboot(EC_REBOOT_JUMP_RW, 0); + mdelay(100); + /* Use Hello cmd to "reset" EC now in RW mode */ + google_chromeec_hello(); + /* re-run version command & print */ + google_chromeec_get_version(); + } + + /* Enable auto fan control if applicable */ + struct chromeec_command cec_cmd; + cec_cmd.cmd_code = EC_CMD_THERMAL_AUTO_FAN_CTRL; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = NULL; + cec_cmd.cmd_data_out = NULL; + cec_cmd.cmd_size_in = 0; + cec_cmd.cmd_size_out = 0; + cec_cmd.cmd_dev_index = 0; + google_chromeec_command(&cec_cmd); +} + int google_chromeec_get_num_pd_ports(unsigned int *num_ports) { struct ec_response_usb_pd_ports resp = {}; @@ -1427,14 +1469,405 @@ int google_chromeec_get_pd_port_caps(int port, return 0; } -void google_chromeec_init(void) +int google_ec_running_ro(void) { - google_chromeec_log_uptimeinfo(); + return (google_chromeec_get_current_image() == EC_IMAGE_RO); } -int google_ec_running_ro(void) +void google_chromeec_reboot_ro(void) { - return (google_chromeec_get_current_image() == EC_IMAGE_RO); + /* Reboot the EC and make it come back in RO mode */ + printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); + post_code(0); /* clear current post code */ + google_chromeec_reboot(EC_REBOOT_COLD, 0); + udelay(1000); + board_reset(); + halt(); +} + +/* Timeout waiting for EC hash calculation completion */ +static const int CROS_EC_HASH_TIMEOUT_MS = 2000; + +/* Time to delay between polling status of EC hash calculation */ +static const int CROS_EC_HASH_CHECK_DELAY_MS = 10; + +int google_chromeec_swsync(void) +{ + static struct ec_response_vboot_hash resp; + uint8_t *ec_hash; + int ec_hash_size; + uint8_t *ecrw_hash, *ecrw; + int need_update = 0, i; + size_t ecrw_size; + + /* skip if on S3 resume path */ + if (acpi_is_wakeup_s3()) + return 0; + + /* Get EC_RW hash from CBFS */ + ecrw_hash = cbfs_map("ecrw.hash", NULL); + + if (!ecrw_hash) { + /* Assume no EC update file for this board */ + printk(BIOS_DEBUG, "ChromeEC SW Sync: no EC_RW update available\n"); + return 0; + } + + /* Got an expected hash */ + printk(BIOS_DEBUG, "ChromeEC SW Sync: Expected hash: "); + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + printk(BIOS_DEBUG, "%02x", ecrw_hash[i]); + printk(BIOS_DEBUG, "\n"); + + /* Get hash of current EC-RW */ + if (google_chromeec_read_hash(&resp)) { + printk(BIOS_ERR, "Failed to read current EC_RW hash.\n"); + return -1; + } + ec_hash = resp.hash_digest; + ec_hash_size = resp.digest_size; + /* Check hash size */ + if (ec_hash_size != SHA256_DIGEST_SIZE) { + printk(BIOS_ERR, "ChromeEC SW Sync: - " + "read_hash says size %d, not %d\n", + ec_hash_size, SHA256_DIGEST_SIZE); + return -1; + } + + /* We got a proper hash */ + printk(BIOS_DEBUG, "ChromeEC SW Sync: current EC_RW hash: "); + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + printk(BIOS_DEBUG, "%02x", ec_hash[i]); + printk(BIOS_DEBUG, "\n"); + + /* compare hashes */ + need_update = SafeMemcmp(ec_hash, ecrw_hash, SHA256_DIGEST_SIZE); + + /* If in RW and need to update, return/reboot to RO */ + if (need_update && google_chromeec_get_current_image() == EC_IMAGE_RW + && !CONFIG(SOC_INTEL_CSE_LITE_SKU) && !CONFIG(BOARD_GOOGLE_BASEBOARD_FIZZ)) { + printk(BIOS_DEBUG, "ChromeEC SW Sync: EC_RW needs update but in RW; rebooting to RO\n"); + google_chromeec_reboot_ro(); + return -1; + } + + /* Update EC if necessary */ + if (need_update) { + printk(BIOS_DEBUG, "ChromeEC SW Sync: updating EC_RW...\n"); + + /* Get ecrw image from CBFS */ + ecrw = cbfs_map("ecrw", &ecrw_size); + if (!ecrw) { + printk(BIOS_ERR, "ChromeEC SW Sync: no ecrw image found in CBFS; cannot update\n"); + return -1; + } + + if (google_chromeec_flash_update_rw(ecrw, ecrw_size)) { + printk(BIOS_ERR, "ChromeEC SW Sync: Failed to update EC_RW.\n"); + return -1; + } + + /* Boards which jump to EC-RW early need a full reset here */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + google_chromeec_reboot_ro(); + } + + /* Have EC recompute hash for new EC_RW block */ + if (google_chromeec_read_hash(&resp) ) { + printk(BIOS_ERR, "ChromeEC SW Sync: Failed to read new EC_RW hash.\n"); + return -1; + } + + /* Compare new EC_RW hash to value from CBFS */ + ec_hash = resp.hash_digest; + if(SafeMemcmp(ec_hash, ecrw_hash, SHA256_DIGEST_SIZE)) { + /* hash mismatch! */ + printk(BIOS_DEBUG, "ChromeEC SW Sync: Expected hash: "); + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + printk(BIOS_DEBUG, "%02x", ecrw_hash[i]); + printk(BIOS_DEBUG, "\n"); + printk(BIOS_DEBUG, "ChromeEC SW Sync: EC hash: "); + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + printk(BIOS_DEBUG, "%02x", ec_hash[i]); + printk(BIOS_DEBUG, "\n"); + return -1; + } + printk(BIOS_DEBUG, "ChromeEC SW Sync: EC_RW hashes match\n"); + printk(BIOS_DEBUG, "ChromeEC SW Sync: done\n"); + } else { + printk(BIOS_DEBUG, "ChromeEC SW Sync: EC_RW is up to date\n"); + } + + return 0; +} + +int google_chromeec_read_hash(struct ec_response_vboot_hash *hash) +{ + struct chromeec_command cec_cmd; + struct ec_params_vboot_hash p; + int recalc_requested = 0; + uint64_t start = timer_us(0); + + do { + /* Get hash if available. */ + p.cmd = EC_VBOOT_HASH_GET; + cec_cmd.cmd_code = EC_CMD_VBOOT_HASH; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = &p; + cec_cmd.cmd_data_out = hash; + cec_cmd.cmd_size_in = sizeof(p); + cec_cmd.cmd_size_out = sizeof(*hash); + cec_cmd.cmd_dev_index = 0; + printk(BIOS_DEBUG, "ChromeEC: Getting hash:\n"); + if (google_chromeec_command(&cec_cmd)) + return -1; + + switch (hash->status) { + case EC_VBOOT_HASH_STATUS_NONE: + /* We have no valid hash - let's request a recalc + * if we haven't done so yet. */ + if (recalc_requested != 0) { + mdelay(CROS_EC_HASH_CHECK_DELAY_MS); + break; + } + printk(BIOS_DEBUG, "ChromeEC: No valid hash (status=%d size=%d). " + "Compute one...\n", hash->status, hash->size); + p.cmd = EC_VBOOT_HASH_RECALC; + p.hash_type = EC_VBOOT_HASH_TYPE_SHA256; + p.nonce_size = 0; + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + p.offset = EC_VBOOT_HASH_OFFSET_UPDATE; + } else { + p.offset = EC_VBOOT_HASH_OFFSET_RW; + } + p.size = 0; + cec_cmd.cmd_code = EC_CMD_VBOOT_HASH; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = &p; + cec_cmd.cmd_data_out = hash; + cec_cmd.cmd_size_in = sizeof(p); + cec_cmd.cmd_size_out = sizeof(*hash); + cec_cmd.cmd_dev_index = 0; + printk(BIOS_DEBUG, "ChromeEC: Starting EC hash:\n"); + if (google_chromeec_command(&cec_cmd)) + return -1; + recalc_requested = 1; + /* Command will wait to return until hash is done/ready */ + break; + case EC_VBOOT_HASH_STATUS_BUSY: + /* Hash is still calculating. */ + mdelay(CROS_EC_HASH_CHECK_DELAY_MS); + break; + case EC_VBOOT_HASH_STATUS_DONE: + default: + /* We have a valid hash. */ + break; + } + } while (hash->status != EC_VBOOT_HASH_STATUS_DONE && + timer_us(start) < CROS_EC_HASH_TIMEOUT_MS * 1000); + if (hash->status != EC_VBOOT_HASH_STATUS_DONE) { + printk(BIOS_DEBUG, "ChromeEC: Hash status not done: %d\n", hash->status); + return -1; + } + return 0; +} + +int google_chromeec_flash_update_rw(const uint8_t *image, int image_size) +{ + uint32_t rw_offset, rw_size; + int ret; + enum ec_flash_region region; + + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + region = EC_FLASH_REGION_UPDATE; + } else { + region = EC_FLASH_REGION_RW; + } + + /* get max size that can be written, offset to write */ + if (google_chromeec_flash_offset(region, &rw_offset, &rw_size)) + return -1; + if (image_size > rw_size) { + printk(BIOS_ERR, "Image size (%d) greater than flash region size (%d)\n", + image_size, rw_size); + return -1; + } + + /* + * Erase the entire RW section, so that the EC doesn't see any garbage + * past the new image if it's smaller than the current image. + * + */ + ret = google_chromeec_flash_erase(rw_offset, rw_size); + if (ret) + return ret; + /* Write the image */ + return(google_chromeec_flash_write(image, rw_offset, image_size)); +} + +int google_chromeec_flash_offset(enum ec_flash_region region, + uint32_t *offset, uint32_t *size) +{ + struct chromeec_command cec_cmd; + struct ec_params_flash_region_info p; + struct ec_response_flash_region_info r; + p.region = region; + + /* Get offset and size */ + cec_cmd.cmd_code = EC_CMD_FLASH_REGION_INFO; + cec_cmd.cmd_version = EC_VER_FLASH_REGION_INFO; + cec_cmd.cmd_data_in = &p; + cec_cmd.cmd_data_out = &r; + cec_cmd.cmd_size_in = sizeof(p); + cec_cmd.cmd_size_out = sizeof(r); + cec_cmd.cmd_dev_index = 0; + printk(BIOS_DEBUG, "Getting EC region info\n"); + if (google_chromeec_command(&cec_cmd)) + return -1; + + if (offset) + *offset = r.offset; + if (size) + *size = r.size; + return 0; +} + +static uint32_t burst = 0; + +int google_chromeec_flash_write(const uint8_t *data, uint32_t offset, uint32_t size) +{ + //printk(BIOS_DEBUG, "google_chromeec_flash_write(): 0x%x bytes at 0x%x\n", size, offset); + burst = google_chromeec_flash_write_burst_size(); + uint32_t end, off; + int ret; + if (!burst) + return -1; + end = offset + size; + printk(BIOS_DEBUG, "Writing EC RW region\n"); + for (off = offset; off < end; off += burst, data += burst) { + uint32_t todo = MIN(end - off, burst); + if (todo < burst) { + uint8_t *buf = malloc(burst); + memcpy(buf, data, todo); + // Pad the buffer with a decent guess for erased data + // value. + memset(buf + todo, 0xff, burst - todo); + ret = google_chromeec_flash_write_block_old(buf, + off, burst); + free(buf); + } else { + ret = google_chromeec_flash_write_block_old(data, + off, burst); + } + if (ret) + return ret; + } + return 0; +} + +/** + * Return optimal flash write burst size + */ +int google_chromeec_flash_write_burst_size(void) +{ + struct chromeec_command cec_cmd; + struct ec_response_flash_info info; + uint32_t pdata_max_size = EC_LPC_HOST_PACKET_SIZE - sizeof(struct ec_host_request) - + sizeof(struct ec_params_flash_write); + + /* + * Determine whether we can use version 1 of the command with more + * data, or only version 0. + */ + if (!google_chromeec_cmd_version_supported(EC_CMD_FLASH_WRITE, EC_VER_FLASH_WRITE)) + return EC_FLASH_WRITE_VER0_SIZE; + + /* + * Determine step size. This must be a multiple of the write block + * size, and must also fit into the host parameter buffer. + */ + cec_cmd.cmd_code = EC_CMD_FLASH_INFO; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = NULL; + cec_cmd.cmd_data_out = &info; + cec_cmd.cmd_size_in = 0; + cec_cmd.cmd_size_out = sizeof(info); + cec_cmd.cmd_dev_index = 0; + if (google_chromeec_command(&cec_cmd)) + return -1; + + return (pdata_max_size / info.write_block_size) * + info.write_block_size; +} + +static uint8_t *buf = NULL; +static uint32_t bufsize = 0; + +/** + * Write a single block to the flash + * + * Write a block of data to the EC flash. The size must not exceed the flash + * write block size which you can obtain from cros_ec_flash_write_burst_size(). + * + * The offset starts at 0. You can obtain the region information from + * cros_ec_flash_offset() to find out where to write for a particular region. + * + * Attempting to write to the region where the EC is currently running from + * will result in an error. + * + * @param data Pointer to data buffer to write + * @param offset Offset within flash to write to. + * @param size Number of bytes to write + * @return 0 if ok, -1 on error + */ +int google_chromeec_flash_write_block_old(const uint8_t *data, + uint32_t offset, uint32_t size) +{ + struct chromeec_command cec_cmd; + struct ec_params_flash_write *p; + + assert(data); + /* Make sure request fits in the allowed packet size */ + if (bufsize == 0) { + bufsize = sizeof(*p) + size; + buf = malloc(bufsize); + } else if (bufsize != sizeof(*p) + size) { + free(buf); + bufsize = sizeof(*p) + size; + buf = malloc(bufsize); + } + if (bufsize > EC_LPC_HOST_PACKET_SIZE) + return -1; + + p = (struct ec_params_flash_write *)buf; + p->offset = offset; + p->size = size; + memcpy(p + 1, data, size); + + cec_cmd.cmd_code = EC_CMD_FLASH_WRITE; + cec_cmd.cmd_version = burst == EC_FLASH_WRITE_VER0_SIZE ? 0 : EC_VER_FLASH_WRITE; + cec_cmd.cmd_data_in = buf; + cec_cmd.cmd_data_out = NULL; + cec_cmd.cmd_size_in = bufsize; + cec_cmd.cmd_size_out = 0; + cec_cmd.cmd_dev_index = 0; + + return google_chromeec_command(&cec_cmd); +} + +/** + * Return non-zero if the EC supports the command and version + * + * @param cmd Command to check + * @param ver Version to check + * @return non-zero if command version supported; 0 if not. + */ +int google_chromeec_cmd_version_supported(int cmd, int ver) +{ + uint32_t mask = 0; + if (google_chromeec_get_cmd_versions(cmd, &mask)) + return 0; + return (mask & EC_VER_MASK(ver)) ? 1 : 0; } /* Returns data role and type of device connected */ diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 42326601e8a..964cca25f00 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -353,6 +353,21 @@ struct usb_pd_port_caps { */ int google_chromeec_get_pd_port_caps(int port, struct usb_pd_port_caps *port_caps); +#define SHA256_DIGEST_SIZE 32 + +void google_chromeec_reboot_ro(void); +void google_chromeec_reboot_rw(void); + +int google_chromeec_swsync(void); +int google_chromeec_read_hash(struct ec_response_vboot_hash *hash); +int google_chromeec_flash_update_rw(const uint8_t *image, int image_size); +int google_chromeec_flash_offset(enum ec_flash_region region, + uint32_t *offset, uint32_t *size); +int google_chromeec_flash_write(const uint8_t *data, uint32_t offset, uint32_t size); +int google_chromeec_flash_write_burst_size(void); +int google_chromeec_flash_write_block_old(const uint8_t *data, + uint32_t offset, uint32_t size); +int google_chromeec_cmd_version_supported(int cmd, int ver); /** * Get the keyboard configuration / layout information from EC diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 69b10784b34..4b16ccc5e3f 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -239,7 +239,7 @@ static void fill_ssdt_ps2_keyboard(const struct device *dev) if (google_chromeec_get_keybd_config(&keybd) || !keybd.num_top_row_keys || keybd.num_top_row_keys > MAX_TOP_ROW_KEYS) { - printk(BIOS_ERR, "PS2K: Bad resp from EC. Vivaldi disabled!\n"); + printk(BIOS_INFO, "PS2K: Unsupported or bad resp from EC. Vivaldi disabled!\n"); return; } @@ -252,6 +252,13 @@ static void fill_ssdt_ps2_keyboard(const struct device *dev) !!(keybd.capabilities & KEYBD_CAP_FUNCTION_KEYS), !!(keybd.capabilities & KEYBD_CAP_NUMERIC_KEYPAD), !!(keybd.capabilities & KEYBD_CAP_SCRNLOCK_KEY)); + + /* add a copy under CKSC as well for coolstar's Windows divers */ + acpigen_ps2_keyboard_dsd("_SB.PCI0.LPCB.EC0.CREC.CKSC", keybd.num_top_row_keys, + ps2_action_keys, + !!(keybd.capabilities & KEYBD_CAP_FUNCTION_KEYS), + !!(keybd.capabilities & KEYBD_CAP_NUMERIC_KEYPAD), + !!(keybd.capabilities & KEYBD_CAP_SCRNLOCK_KEY)); } static const char *ec_acpi_name(const struct device *dev) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 080b95da445..36d3ee29fa8 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -94,8 +94,8 @@ static inline u8 write_byte(u8 val, u16 port) static int google_chromeec_status_check(u16 port, u8 mask, u8 cond) { struct stopwatch timeout_sw; - /* One second is more than plenty for any EC operation to complete */ - const uint64_t ec_status_timeout_us = 1 * USECS_PER_SEC; + /* Two seconds is more than plenty for any EC operation to complete */ + const uint64_t ec_status_timeout_us = 2 * USECS_PER_SEC; /* Wait 1 usec between read attempts */ const uint64_t ec_status_read_period_us = 1; diff --git a/src/ec/google/chromeec/utility.c b/src/ec/google/chromeec/utility.c new file mode 100644 index 00000000000..3448265d993 --- /dev/null +++ b/src/ec/google/chromeec/utility.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "utility.h" + +int SafeMemcmp(const void *s1, const void *s2, size_t n) +{ + const unsigned char *us1 = s1; + const unsigned char *us2 = s2; + int result = 0; + + if (0 == n) + return 0; + + /* + * Code snippet without data-dependent branch due to Nate Lawson + * (nate@root.org) of Root Labs. + */ + while (n--) + result |= *us1++ ^ *us2++; + + return result != 0; +} + +long timer_us(long startTime) +{ + struct mono_time now; + timer_monotonic_get(&now); + return (now.microseconds - startTime); +} diff --git a/src/ec/google/chromeec/utility.h b/src/ec/google/chromeec/utility.h new file mode 100644 index 00000000000..d832b6a1c40 --- /dev/null +++ b/src/ec/google/chromeec/utility.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/** + * Compare [n] bytes starting at [s1] with [s2] and return 0 if they + * match, 1 if they don't. Returns 0 if n=0, since no bytes mismatched. + * + * Time taken to perform the comparison is only dependent on [n] and + * not on the relationship of the match between [s1] and [s2]. + * + * Note that unlike Memcmp(), this only indicates inequality, not + * whether s1 is less than or greater than s2. + */ +int SafeMemcmp(const void *s1, const void *s2, size_t n); + +long timer_us(long startTime); diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index 6de72e817d0..210f773c7ed 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -116,3 +116,16 @@ Method (PATX, 0, Serialized) /* Clear sensor events */ W (DWTQ, Local0) } + +/* + * Read current Device DPTF Profile Number + */ +Method (RCDP, 0, NotSerialized) +{ + Local0 = R(DTRI) + If (Local0 == 0) { + Return (R(OTBL)) + } else { + Return (Local0 - 1) + } +} diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 3a9256eb093..bce3441d87c 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -124,6 +124,8 @@ Device (EC0) */ Method (R, 1, Serialized, 2) { + /* Set read operation */ + Arg0[2] = 0 Return (ECRW (Arg0, 0)) } @@ -134,6 +136,8 @@ Device (EC0) */ Method (W, 2, Serialized, 2) { + /* Set write operation */ + Arg0[2] = 1 Return (ECRW (Arg0, Arg1)) } diff --git a/src/ec/quanta/ene_kb3940q/acpi/superio.asl b/src/ec/quanta/ene_kb3940q/acpi/superio.asl index b5962f02670..8ace6dd01e9 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/superio.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/superio.asl @@ -3,9 +3,8 @@ // Scope is \_SB.PCI0.LPCB Device (SIO) { + Name (_HID, EisaId("PNP0A05")) Name (_UID, 0) - Name (_ADR, 0) - #ifdef SIO_EC_ENABLE_PS2K Device (PS2K) // Keyboard diff --git a/src/ec/quanta/it8518/acpi/superio.asl b/src/ec/quanta/it8518/acpi/superio.asl index b91324ded34..9519f35010f 100644 --- a/src/ec/quanta/it8518/acpi/superio.asl +++ b/src/ec/quanta/it8518/acpi/superio.asl @@ -31,7 +31,8 @@ Device (SIO) #ifdef SIO_ENABLE_PS2M Device (PS2M) // Mouse { - Name (_HID, EISAID("PNP0F13")) + Name (_HID, EISAID("LEN2011")) + Name (_CID, EISAID("PNP0F13")) Method (_STA, 0, NotSerialized) { diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 79149675cc4..070a365b545 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -23,6 +23,7 @@ #define APM_CNT_ROUTE_ALL_XHCI 0xca #define APM_CNT_FINALIZE 0xcb #define APM_CNT_LEGACY 0xcc +#define APM_CNT_END_OF_DXE 0xcd #define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_SMMINFO 0xec #define APM_CNT_SMMSTORE 0xed diff --git a/src/include/string.h b/src/include/string.h index 92ea5e5f7f7..21c8fdf5765 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -7,6 +7,10 @@ #include #include /* IWYU pragma: export */ +/* Convert 8-bit char to 16-bit */ +#define STR16_(str) (u ## str) +#define STR16(str) STR16_(str) + void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); diff --git a/src/mainboard/google/auron/acpi/superio.asl b/src/mainboard/google/auron/acpi/superio.asl index e3a31bc657b..42eaba1825c 100644 --- a/src/mainboard/google/auron/acpi/superio.asl +++ b/src/mainboard/google/auron/acpi/superio.asl @@ -6,7 +6,6 @@ #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources #define SIO_EC_HOST_ENABLE // EC Host Interface Resources #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 /* ACPI code for EC SuperIO functions */ #include diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 2ded45256d8..930a891d541 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -17,7 +17,7 @@ chip soc/intel/broadwell chip cpu/intel/haswell device cpu_cluster 0 on ops broadwell_cpu_bus_ops end - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" end device domain 0 on diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 6fa95e8dff3..cc10d97a007 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -77,6 +77,7 @@ void mainboard_smi_sleep(u8 slp_typ) /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); break; + case ACPI_S4: case ACPI_S5: if (gnvs->s5u0 == 0) { google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index 3463028bbdf..e71a5e6ea0d 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -141,11 +141,7 @@ Scope (\_TZ) } Method (_AC4) { - If (\FLVL <= 4) { - Return (CTOK (FAN4_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN4_THRESHOLD_ON)) - } + Return (CTOK (0)) } Name (_AL0, Package () { FAN0 }) diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 33f4b6bf3d5..0df98bff955 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -19,8 +19,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; - gnvs->f4of = FAN4_THRESHOLD_OFF; - gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; gnvs->f3of = FAN3_THRESHOLD_OFF; diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index cdaab35b54e..15187f38d9c 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -84,6 +84,7 @@ chip northbridge/intel/haswell register "peci_tmpin" = "3" # Enable FAN2 register "fan2_enable" = "true" + register "fan2_speed" = "0x47" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h index f4c04743291..3bf0f6aa348 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h @@ -3,29 +3,27 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 35 -#define FAN3_THRESHOLD_ON 40 -#define FAN3_PWM 0x88 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x68 /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 44 -#define FAN2_THRESHOLD_ON 48 -#define FAN2_PWM 0x94 +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0x84 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 53 -#define FAN1_THRESHOLD_ON 58 -#define FAN1_PWM 0xb5 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa5 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 65 -#define FAN0_THRESHOLD_ON 70 +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 #define FAN0_PWM 0xc4 /* Temperature which OS will shutdown at */ diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h index c2a2ef09b87..edde804e3b0 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h @@ -3,30 +3,28 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 45 -#define FAN3_THRESHOLD_ON 58 -#define FAN3_PWM 0x40 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x68 /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0x84 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 59 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb3 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa3 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 79 -#define FAN0_PWM 0xff +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xc4 /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 98 diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h index 27c6c337568..e953fd62ffc 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h @@ -3,10 +3,8 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 40 @@ -14,19 +12,19 @@ #define FAN3_PWM 0x6b /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 75 -#define FAN2_THRESHOLD_ON 83 -#define FAN2_PWM 0xcc +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0x86 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 86 -#define FAN1_THRESHOLD_ON 90 -#define FAN1_PWM 0xe5 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa8 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 93 -#define FAN0_THRESHOLD_ON 96 -#define FAN0_PWM 0xff +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h index 68db6b89e6e..6842ec2b5f9 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h @@ -3,30 +3,28 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 50 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x76 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 59 -#define FAN2_THRESHOLD_ON 65 -#define FAN2_PWM 0x98 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 68 -#define FAN1_THRESHOLD_ON 75 -#define FAN1_PWM 0xbf - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 80 -#define FAN0_THRESHOLD_ON 86 -#define FAN0_PWM 0xdc +/* Fan is at default speed: ~2600 rpm */ +#define FAN4_PWM 0x4b + +/* Fan is at LOW speed: ~3000 rpm */ +#define FAN3_THRESHOLD_OFF 30 +#define FAN3_THRESHOLD_ON 40 +#define FAN3_PWM 0x5B + +/* Fan is at MEDIUM speed: ~4000 rpm */ +#define FAN2_THRESHOLD_OFF 40 +#define FAN2_THRESHOLD_ON 50 +#define FAN2_PWM 0x87 + +/* Fan is at HIGH speed: ~5000 rpm */ +#define FAN1_THRESHOLD_OFF 50 +#define FAN1_THRESHOLD_ON 60 +#define FAN1_PWM 0xc3 + +/* Fan is at FULL speed: ~6000 rpm */ +#define FAN0_THRESHOLD_OFF 60 +#define FAN0_THRESHOLD_ON 70 +#define FAN0_PWM 0xff /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 98 diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h index 5006b649832..1d9f021ff14 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h @@ -3,30 +3,28 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x4c +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 52 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 #define FAN3_PWM 0x6d /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 50 -#define FAN2_THRESHOLD_ON 55 +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 #define FAN2_PWM 0x7c /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 52 -#define FAN1_THRESHOLD_ON 58 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 #define FAN1_PWM 0xa3 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 55 -#define FAN0_THRESHOLD_ON 60 -#define FAN0_PWM 0xba +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 98 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index a7f459454a0..e946c189094 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -27,6 +27,7 @@ config BOARD_GOOGLE_BRYA_COMMON select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select I2C_TPM + select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 @@ -41,9 +42,11 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_GOOGLE_BRYA_COMMON select BOARD_ROMSIZE_KB_32768 + select DRIVERS_AUDIO_SOF select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_ALDERLAKE_S3 select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 @@ -59,6 +62,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_ALDERLAKE_S3 select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select TPM_GOOGLE_CR50 select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG @@ -72,6 +76,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA select MAINBOARD_DISABLE_STAGE_CACHE select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_ALDERLAKE_S3 select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE select SYSTEM_TYPE_LAPTOP @@ -85,6 +90,7 @@ config BOARD_GOOGLE_BASEBOARD_SKOLAS select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_ALDERLAKE_S3 select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SOC_INTEL_RAPTORLAKE select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 567985b4956..6969ff6cdd9 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -57,16 +57,16 @@ config BOARD_GOOGLE_FELWINTER config BOARD_GOOGLE_GIMBLE bool "-> Gimble" select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS - select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select CHROMEOS_DSM_CALIB + select CHROMEOS_DSM_PARAM_FILE_NAME select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_MAX98390 config BOARD_GOOGLE_GIMBLE4ES bool "-> Gimble4ES" select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS - select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select CHROMEOS_DSM_CALIB + select CHROMEOS_DSM_PARAM_FILE_NAME select DEFAULT_ADL_NEM select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_MAX98390 @@ -118,7 +118,7 @@ config BOARD_GOOGLE_PRIMUS4ES config BOARD_GOOGLE_REDRIX bool "-> Redrix" select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_CALIB select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_GFX_GENERIC @@ -130,7 +130,7 @@ config BOARD_GOOGLE_REDRIX config BOARD_GOOGLE_REDRIX4ES bool "-> Redrix4ES" select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_CALIB select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS select DEFAULT_ADL_NEM select DRIVERS_GENESYSLOGIC_GL9755 diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 7a730b74bf4..4c1574e55f4 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -26,6 +26,7 @@ DefinitionBlock( #include #include #include + #include } } diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index faed00d04ca..8fa8ea6ad34 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -275,6 +275,12 @@ chip soc/intel/alderlake register "sdmode_delay" = "5" device generic 0 on end end + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm1" + device generic 0 on end + end end device ref gspi1 off end device ref pch_espi on diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 38535a47732..f9ece23a738 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # DPTF enable register "dptf_enable" = "1" @@ -106,7 +106,9 @@ chip soc/intel/alderlake }" device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref dtt on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index efc2fcbc988..835cd1d4f4c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # DPTF enable register "dptf_enable" = "1" @@ -153,6 +153,7 @@ chip soc/intel/alderlake .backlight_off_delay_ms = 200, .backlight_pwm_hz = 200, }" + register "gfx" = "GMA_DEFAULT_PANEL(0)" end device ref dtt on end device ref tbt_pcie_rp0 on end @@ -196,6 +197,13 @@ chip soc/intel/alderlake device pnp 0c09.0 on end end end - device ref hda on end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 16c7ce02df2..ee31f741b7b 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # DPTF enable register "dptf_enable" = "1" @@ -153,7 +153,9 @@ chip soc/intel/alderlake }" device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref dtt on end device ref tcss_xhci on end device ref xhci on end diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb index 6ca0c9e1b51..b88872cdd37 100644 --- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # DPTF enable register "dptf_enable" = "1" @@ -127,7 +127,9 @@ chip soc/intel/alderlake }" device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref dtt on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index e0a3f3d7ba9..087b7b1a029 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -316,6 +316,12 @@ chip soc/intel/alderlake register "sdmode_delay" = "5" device generic 0 on end end + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm1" + device generic 0 on end + end end device ref pch_espi on chip ec/google/chromeec diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 2eca4499a89..46ce167e857 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -558,5 +558,13 @@ chip soc/intel/alderlake end end end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98373" + register "jack_tplg" = "nau8825" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb index 702c8b13763..5f46ad1a67d 100644 --- a/src/mainboard/google/brya/variants/osiris/overridetree.cb +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -239,6 +239,12 @@ chip soc/intel/alderlake probe AUDIO MAX98360_NAU88L25B_I2S end end + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "nau8825" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end device ref pcie_rp6 off end # PCIE6 WWAN device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 3f4a6ac38ad..126f171a593 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -502,6 +502,12 @@ chip soc/intel/alderlake probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S end end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end device ref pcie_rp5 on chip soc/intel/common/block/pcie/rtd3 diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index e2481a19901..001e2b2cd86 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -368,6 +368,12 @@ chip soc/intel/alderlake probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S end end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end device ref pcie_rp5 on chip soc/intel/common/block/pcie/rtd3 diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 7531a8d7bdc..b90c8de74ca 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -335,6 +335,12 @@ chip soc/intel/alderlake probe AUDIO AUDIO_MAX98357_ALC5682I_I2S_2WAY end end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end device ref pcie_rp5 on chip soc/intel/common/block/pcie/rtd3 diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index 956e74c2181..0f2de60ff09 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -419,5 +419,13 @@ chip soc/intel/alderlake end end end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98373" + register "jack_tplg" = "nau8825" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl index 3552e29ad85..f96dc11b009 100644 --- a/src/mainboard/google/butterfly/acpi/mainboard.asl +++ b/src/mainboard/google/butterfly/acpi/mainboard.asl @@ -15,11 +15,9 @@ Scope (\_SB) { Device (TPAD) { - Name (_UID, 1) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name(_HID, EisaId("PNP0C0E")) + Name(_HID, "CYSM0000") + Name(_UID, 1) + Name(_HRV, 2) // Trackpad Wake is GPIO11, wake from S3 Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) @@ -27,7 +25,7 @@ Scope (\_SB) { Name(_CRS, ResourceTemplate() { // PIRQG -> GSI22 - Interrupt (ResourceConsumer, EDGE, ActiveLow) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) { BOARD_TRACKPAD_IRQ } diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index dd68904f9be..f526fc12da6 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -9,6 +9,7 @@ Scope (\_SB.PCI0.I2C2) Name (_CID, AUDIO_CODEC_CID) Name (_DDN, AUDIO_CODEC_DDN) Name (_UID, 1) + Name (_HRV, 0x02) /* Add DT style bindings with _DSD */ Name (_DSD, Package () { @@ -31,8 +32,16 @@ Scope (\_SB.PCI0.I2C2) "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ ) + /* For Linux driver */ GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault,, "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } + + /* For coolstar's Windows driver */ + GpioIo (Exclusive, PullNone, 0x0000, 0x0000, IoRestrictionInputOnly, + "\\_SB.GPSE", 0x00, ResourceConsumer, ,) + { + BOARD_JACK_MAXIM_GPIO_INDEX + } } ) Return (SBUF) } @@ -74,7 +83,7 @@ Scope (\_SB.PCI0.I2C2) "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ ) - GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault,, + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } } ) diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl index 14e51354251..22f4d89de65 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -36,8 +36,6 @@ Scope (\_SB.PCI0.I2C1) } } - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - /* Allow device to power off in S0 */ Name (_S0W, 4) } diff --git a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl index 6fc1e107d4d..2d6daea59ce 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl @@ -35,8 +35,6 @@ Scope (\_SB.PCI0.I2C1) } } - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - /* Allow device to power off in S0 */ Name (_S0W, 4) } diff --git a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl index 02b4db3e9d7..5c0ccebde72 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl @@ -77,8 +77,6 @@ Scope (\_SB.PCI0.I2C1) } } - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - /* Allow device to power off in S0 */ Name (_S0W, 4) } diff --git a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl index 43180a2bea9..d0aa88345d4 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl @@ -8,7 +8,6 @@ Scope (\_SB.PCI0.I2C6) Name (_DDN, "Atmel Touchpad") Name (_UID, 2) Name (ISTP, 1) /* Touchpad */ - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) Name (_CRS, ResourceTemplate() { diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl index 93cda3477f3..da42efced32 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_elan.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -31,8 +31,6 @@ Scope (\_SB.PCI0.I2C6) } } - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - /* Allow device to power off in S0 */ Name (_S0W, 4) } diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c968dfc0b76..f53a65e9cc7 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -99,7 +99,7 @@ chip soc/intel/braswell device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - Signal Processing Controller + device pci 0b.0 off end # 8086 22dc - Signal Processing Controller device pci 10.0 on end # 8086 2294 - MMC Port device pci 11.0 off end # 8086 0F15 - SDIO Port device pci 12.0 on end # 8086 0F16 - SD Port @@ -124,7 +124,7 @@ chip soc/intel/braswell device pci 1e.0 on end # 8086 2286 - SIO - DMA device pci 1e.1 off end # 8086 0F08 - PWM 1 device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.3 off end # 8086 228a - HSUART 1 device pci 1e.4 off end # 8086 228c - HSUART 2 device pci 1e.5 on end # 8086 228e - SPI 1 device pci 1e.6 off end # 8086 2290 - SPI 2 diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 7394b78b68c..18d5f91cbd0 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -76,6 +76,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + case ACPI_S4: case ACPI_S5: if (gnvs->s5u0 == 0) google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index ca72da1ac4b..ca8f1618ee4 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 + select DRIVERS_AUDIO_SOF select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_CS42L42 select DRIVERS_I2C_GENERIC @@ -19,6 +20,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 56812d5a203..c99f4c76c3e 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -23,6 +23,7 @@ DefinitionBlock( { #include #include + #include } } diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2124dc4cb17..48ad65f2f22 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -150,7 +150,7 @@ chip soc/intel/jasperlake register "SdCardPowerEnableActiveHigh" = "1" # Enable S0ix support - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Display related UPDs # Select eDP for port A @@ -208,7 +208,9 @@ chip soc/intel/jasperlake device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end # Integrated Graphics Device device pci 04.0 on # Default DPTF Policy for all Dedede boards if not overridden chip drivers/intel/dptf @@ -384,7 +386,33 @@ chip soc/intel/jasperlake end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 off end # Intel HDA/cAVS + device pci 1f.3 on + chip drivers/sof + register "spkr_tplg" = "rt1015" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on + probe AUDIO_AMP RT1015_I2C + probe AUDIO_AMP RT1015P_AUTO + end + end + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on + probe AUDIO_AMP MAX98360 + end + end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on + probe AUDIO_AMP UNPROVISIONED + end + end + end # Intel HDA/cAVS device pci 1f.4 off end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.7 off end # Intel Trace Hub diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index bb5bf24419b..8fe65ddb1b2 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -367,7 +367,6 @@ chip soc/intel/jasperlake register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" device i2c 36 on - probe CAMERA_WFC CAMERA_UNPROVISIONED probe CAMERA_WFC CAMERA_OVTI5675 end end @@ -425,7 +424,6 @@ chip soc/intel/jasperlake register "vcm_compat" = ""dongwoon,dw9714"" device i2c 0C on - probe CAMERA_VCM CAMERA_VCM_UNPROVISIONED probe CAMERA_VCM CAMERA_VCM0 end end @@ -444,7 +442,9 @@ chip soc/intel/jasperlake register "nvm_width" = "0x10" register "nvm_compat" = ""atmel,24c08"" - device i2c 50 on end + device i2c 50 on + probe CAMERA_VCM CAMERA_VCM0 + end end end device pci 19.0 on diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 6e9bf02136e..0f503dffd9b 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -22,6 +22,7 @@ DefinitionBlock( { #include #include + #include } /* Per board variant mainboard hooks. */ #include diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d819ca7ee83..4657cebcc26 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -39,7 +39,7 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" register "dptf_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 25, @@ -222,6 +222,7 @@ chip soc/intel/cannonlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on + register "gfx" = "GMA_DEFAULT_PANEL(0)" chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 1e9ffd9255e..a500f84908b 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -305,6 +305,7 @@ chip soc/intel/skylake device pci 15.2 on chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" + register "generic.sub" = ""1AE0006B"" register "generic.desc" = ""Touchpad"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "hid_desc_reg_offset" = "0x1" diff --git a/src/mainboard/google/eve/ec.c b/src/mainboard/google/eve/ec.c index 499f56484bf..eb4e0978fb0 100644 --- a/src/mainboard/google/eve/ec.c +++ b/src/mainboard/google/eve/ec.c @@ -15,4 +15,10 @@ void mainboard_ec_init(void) }; google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + +#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT + /* Turn off keyboard backlight after turning on in romstage */ + if (!acpi_is_wakeup_s3()) + google_chromeec_kbbacklight(0); +#endif } diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index f3c0f1140b4..9aa4d453409 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -2,10 +2,12 @@ #include #include +#include #include #include #include #include "spd/spd.h" +#include "ec.h" void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -41,4 +43,11 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) printk(BIOS_WARNING, "Limiting memory to 1600MHz\n"); mem_cfg->DdrFreqLimit = 1600; } + +#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT + /* Turn on keyboard backlight to indicate we are booting */ + const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME) + google_chromeec_kbbacklight(50); +#endif } diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 8b7811c1a6d..749b43553bf 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -90,7 +90,7 @@ config INCLUDE_NHLT_BLOBS config INCLUDE_NHLT_BLOBS_KARMA bool "Include blobs for karma audio." select NHLT_DA7219 - select NHLT_DMIC_4CH + select NHLT_DMIC_2CH select NHLT_MAX98357 config UART_FOR_CONSOLE @@ -98,7 +98,7 @@ config UART_FOR_CONSOLE default 2 config USE_PM_ACPI_TIMER - default n + default y config EDK2_BOOT_TIMEOUT int diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index b0d94a09d72..68d91aa9735 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -136,6 +136,13 @@ static void mainboard_set_power_limits(struct soc_power_limits_config *conf) conf->tdp_pl4 = SET_PSYSPL2(psyspl2); } + + /* Override PL1/PL2 for i7 KBL-R SKU */ + if (sku & FIZZ_SKU_ID_I7_U42) { + conf->tdp_pl1_override = 20; + pl2 = 40; + } + conf->tdp_pl2_override = pl2; /* set psyspl2 to 90% of max adapter power */ conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); @@ -179,6 +186,24 @@ const char *smbios_system_sku(void) return sku_str; } +const char *smbios_mainboard_product_name(void) +{ + static char product[12]; + + switch (board_oem_id()) + { + case 0: snprintf(product, sizeof(product), "Kench"); break; + case 1: snprintf(product, sizeof(product), "Teemo"); break; + case 2: snprintf(product, sizeof(product), "Sion"); break; + case 3: + case 4: + case 5: snprintf(product, sizeof(product), "Wukong"); break; + case 6: snprintf(product, sizeof(product), "Teemo"); break; + default: snprintf(product, sizeof(product), "UNK Fizz"); break; + } + return product; +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); diff --git a/src/mainboard/google/fizz/variants/fizz/data.vbt b/src/mainboard/google/fizz/variants/fizz/data.vbt index dbbf475f217..66797427bc9 100644 Binary files a/src/mainboard/google/fizz/variants/fizz/data.vbt and b/src/mainboard/google/fizz/variants/fizz/data.vbt differ diff --git a/src/mainboard/google/fizz/variants/karma/nhlt.c b/src/mainboard/google/fizz/variants/karma/nhlt.c index e237d2e1851..75a27d2078d 100644 --- a/src/mainboard/google/fizz/variants/karma/nhlt.c +++ b/src/mainboard/google/fizz/variants/karma/nhlt.c @@ -7,9 +7,9 @@ void variant_nhlt_init(struct nhlt *nhlt) { - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); /* Dialog DA7219 Headset codec. */ if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 631d90d1f32..87b468a7b11 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -51,7 +51,7 @@ config BOARD_GOOGLE_CHELL config BOARD_GOOGLE_GLADOS select BOARD_GOOGLE_BASEBOARD_GLADOS - select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS + select NHLT_DMIC_2CH if INCLUDE_NHLT_BLOBS select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_LARS @@ -67,7 +67,7 @@ config BOARD_GOOGLE_SENTRY select DRIVERS_GENERIC_MAX98357A select INTEL_GMA_HAVE_VBT select MAINBOARD_NO_FSP_GOP - select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS + select NHLT_DMIC_2CH if INCLUDE_NHLT_BLOBS select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 03030598d80..6d1fe78f60a 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -55,7 +55,7 @@ chip soc/amd/cezanne }" # Enable S0i3 support - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Enable STT support register "stt_control" = "1" diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 3522787c3c6..9e7730544a8 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 + select DRIVERS_AUDIO_SOF select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 @@ -43,13 +44,13 @@ config BOARD_GOOGLE_HATCH config BOARD_GOOGLE_HELIOS select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_HELIOS_DISKSWAP select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 select INTEL_GMA_HAVE_VBT @@ -73,13 +74,13 @@ config BOARD_GOOGLE_MUSHU config BOARD_GOOGLE_NIGHTFURY select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_CALIB select DRIVERS_I2C_MAX98390 select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_PALKIA select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 976d82970c8..d240e559f66 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/cannonlake # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Enable DPTF register "dptf_enable" = "1" register "power_limits_config" = "{ @@ -347,7 +347,14 @@ chip soc/intel/cannonlake end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 3f77292c1c7..335ec8b9f03 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -115,9 +115,7 @@ chip soc/intel/cannonlake chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake_gpe" = "GPE0_DW0_08" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index dd5529ac465..34fcdd1adfa 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -125,9 +125,7 @@ chip soc/intel/cannonlake chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake_gpe" = "GPE0_DW0_08" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" @@ -199,5 +197,13 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/sof + register "spkr_tplg" = "rt1011" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index bc49e847a09..78dea3024db 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -137,9 +137,7 @@ chip soc/intel/cannonlake chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake_gpe" = "GPE0_DW0_08" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" @@ -218,6 +216,11 @@ chip soc/intel/cannonlake register "sdmode_delay" = "5" device generic 0 on end end - end # Intel HDA + chip drivers/sof + register "spkr_tplg" = "rt1011" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end end diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 17b79bb3148..d3fe2e09e5e 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -176,9 +176,7 @@ chip soc/intel/cannonlake chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake_gpe" = "GPE0_DW0_08" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 131b91ddd3b..73ecff06b70 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -37,7 +37,7 @@ static const struct pad_config gpio_table[] = { /* C23 : UART2_CTS# ==> NC */ PAD_NC(GPP_C23, NONE), /* D15 : TOUCHSCREEN_RST_L */ - PAD_CFG_GPO(GPP_C12, 1, DEEP), + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* D16 : TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), /* E23 : GPP_E23 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 915b6c36a64..6daa3c66bcf 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -214,9 +214,7 @@ chip soc/intel/cannonlake register "name" = ""PENH"" # GPP_A16 is the IRQ source, and GPP_A8 is the wake source register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_A16)" - register "key.wake_gpe" = "GPE0_DW0_08" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" @@ -266,6 +264,12 @@ chip soc/intel/cannonlake register "sdmode_delay" = "5" device generic 0 on end end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "da7219" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end # Intel HDA end # domain end diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 632b1462ac8..115c90da2cf 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -135,9 +135,7 @@ chip soc/intel/cannonlake chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake_gpe" = "GPE0_DW0_08" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 2d7bf45d444..433abaea424 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -263,5 +263,13 @@ chip soc/intel/cannonlake device pci 1d.5 off end device pci 1a.0 on end #eMMC device pci 1e.3 off end # GSPI #1 + device pci 1f.3 on + chip drivers/sof + register "spkr_tplg" = "max98390" + register "jack_tplg" = "da7219" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end # Intel HDA end # domain end diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index eaf038f4683..1a2f282d331 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -193,6 +193,12 @@ chip soc/intel/cannonlake register "sdmode_delay" = "5" device generic 0 on end end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt1011" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end # Intel I2S end end diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index a4feeb496a1..7ee0f34e6c8 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -26,6 +26,7 @@ void mainboard_smi_sleep(u8 slp_typ) set_gpio(GPIO_USB_CTL_1, 0); } break; + case ACPI_S4: case ACPI_S5: set_power_led(LED_OFF); break; diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h index 7dc48369824..7a988946637 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h @@ -11,22 +11,22 @@ /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 40 #define FAN3_THRESHOLD_ON 50 -#define FAN3_PWM 0x55 +#define FAN3_PWM 0x62 /* Fan is at MEDIUM speed */ #define FAN2_THRESHOLD_OFF 55 #define FAN2_THRESHOLD_ON 67 -#define FAN2_PWM 0xa6 +#define FAN2_PWM 0x86 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 65 -#define FAN1_THRESHOLD_ON 70 -#define FAN1_PWM 0xc0 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa8 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 90 -#define FAN0_THRESHOLD_ON 100 -#define FAN0_PWM 0xff +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 104 diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h index 58ca2f6d98d..bc46ae39b30 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h @@ -9,24 +9,24 @@ #define FAN4_PWM 0x4d /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 42 -#define FAN3_THRESHOLD_ON 47 -#define FAN3_PWM 0xa5 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x62 /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 54 -#define FAN2_THRESHOLD_ON 59 -#define FAN2_PWM 0xb2 +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0x86 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 66 -#define FAN1_THRESHOLD_ON 71 -#define FAN1_PWM 0xc9 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa8 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 78 -#define FAN0_THRESHOLD_ON 83 -#define FAN0_PWM 0xd8 +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 diff --git a/src/mainboard/google/kahlee/variants/aleena/overridetree.cb b/src/mainboard/google/kahlee/variants/aleena/overridetree.cb index c5d484bdc2f..d019dba7cde 100644 --- a/src/mainboard/google/kahlee/variants/aleena/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/overridetree.cb @@ -40,7 +40,6 @@ chip soc/amd/stoneyridge register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "generic.wake" = "7" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end @@ -51,7 +50,7 @@ chip soc/amd/stoneyridge register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index 632ffa3e9a2..0f4d2816453 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -8,7 +8,7 @@ chip soc/amd/stoneyridge }" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" + register "uma_size" = "256 * MiB" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ GPIO_I2C2_SCL | GPIO_I2C3_SCL" @@ -78,7 +78,6 @@ chip soc/amd/stoneyridge register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "wake" = "7" register "detect" = "1" device i2c 15 on end end diff --git a/src/mainboard/google/kahlee/variants/careena/overridetree.cb b/src/mainboard/google/kahlee/variants/careena/overridetree.cb index 666373f1bcb..c9b3036c1d3 100644 --- a/src/mainboard/google/kahlee/variants/careena/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/overridetree.cb @@ -60,7 +60,7 @@ chip soc/amd/stoneyridge register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/grunt/overridetree.cb b/src/mainboard/google/kahlee/variants/grunt/overridetree.cb index 0b155c5a7b7..e1e1402b6e0 100644 --- a/src/mainboard/google/kahlee/variants/grunt/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/overridetree.cb @@ -39,7 +39,7 @@ chip soc/amd/stoneyridge register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/liara/overridetree.cb b/src/mainboard/google/kahlee/variants/liara/overridetree.cb index b5256b52149..269dcc999e9 100644 --- a/src/mainboard/google/kahlee/variants/liara/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/overridetree.cb @@ -45,7 +45,6 @@ chip soc/amd/stoneyridge register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "generic.wake" = "7" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb index 74ab535ea3b..157ab9842af 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb @@ -53,7 +53,6 @@ chip soc/amd/stoneyridge register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "generic.wake" = "7" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end @@ -88,7 +87,7 @@ chip soc/amd/stoneyridge register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/treeya/overridetree.cb b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb index 5c705246d83..e080eb24ffd 100644 --- a/src/mainboard/google/kahlee/variants/treeya/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb @@ -70,7 +70,6 @@ chip soc/amd/stoneyridge register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" - register "generic.wake" = "7" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end @@ -93,7 +92,7 @@ chip soc/amd/stoneyridge register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 2f42b7da181..3ed68b6e2e8 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -54,6 +54,7 @@ void mainboard_smi_sleep(u8 slp_typ) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); break; + case ACPI_S4: case ACPI_S5: if (gnvs->s5u0 == 0) google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 88e37badf62..f00407d558e 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -159,7 +159,6 @@ config UART_FOR_CONSOLE config INCLUDE_NHLT_BLOBS bool "Include blobs for audio" select NHLT_DMIC_2CH_16B - select NHLT_DMIC_4CH_16B select NHLT_MAX98357 config DRIVER_TPM_SPI_BUS diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index abf53b47c53..e8b7c4f2229 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -55,7 +55,7 @@ chip soc/intel/apollolake register "slp_s3_assertion_width_usecs" = "28000" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "0" # Enable DPTF register "dptf_enable" = "1" @@ -115,7 +115,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Gaussian Mixture Model (GMM) + device pci 03.0 off end # - Gaussian Mixture Model (GMM) device pci 0c.0 on chip drivers/wifi/generic register "wake" = "GPE0A_CNVI_PME_STS" @@ -238,7 +238,7 @@ chip soc/intel/apollolake end end end # - XHCI - device pci 15.1 on end # - XDCI + device pci 15.1 off end # - XDCI device pci 16.0 on end # - I2C 0 device pci 16.1 off end # - I2C 1 device pci 16.2 off end # - I2C 2 diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index 320e470c91c..89f16c7b465 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -14,10 +14,6 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) if (!nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_INFO, "Added 2CH DMIC array.\n"); - /* 4 Channel DMIC array. */ - if (!nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_INFO, "Added 4CH DMIC arrays.\n"); - /* * Headset codec is bi-directional but uses the same configuration * settings for render and capture endpoints. diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 7fc07fa6f13..3f2e43c8f24 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -29,11 +29,10 @@ Scope (\_SB) { Device (TPAD) { - Name (_UID, 1) - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name(_HID, EisaId("PNP0C0E")) + Name(_HID, "CYSM0000") + Name(_UID, 1) + Name(_HRV, 2) // Trackpad Wake is GPIO12, wake from S3 Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 3007bcbc9aa..6f1636dad6e 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -47,6 +47,7 @@ config BOARD_GOOGLE_NAMI select DRIVERS_SPI_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select SPI_TPM select SYSTEM_TYPE_LAPTOP @@ -57,6 +58,7 @@ config BOARD_GOOGLE_NAUTILUS select DRIVERS_I2C_DA7219 select I2C_TPM select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select SYSTEM_TYPE_CONVERTIBLE select VARIANT_HAS_CAMERA_ACPI @@ -93,6 +95,7 @@ config BOARD_GOOGLE_SORAKA select DRIVERS_I2C_MAX98927 select I2C_TPM select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select NO_FADT_8042 select SYSTEM_TYPE_DETACHABLE select VARIANT_HAS_CAMERA_ACPI @@ -133,37 +136,36 @@ config DRIVER_TPM_SPI_BUS config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." select NHLT_DMIC_2CH - select NHLT_DMIC_4CH select NHLT_MAX98927 select NHLT_RT5663 config INCLUDE_NHLT_BLOBS_ATLAS bool "Include blobs for atlas audio." select NHLT_DA7219 - select NHLT_DMIC_4CH + select NHLT_DMIC_2CH select NHLT_MAX98373 config INCLUDE_NHLT_BLOBS_NAUTILUS bool "Include blobs for nautilus audio." select NHLT_DA7219 - select NHLT_DMIC_4CH + select NHLT_DMIC_2CH select NHLT_MAX98357 config INCLUDE_NHLT_BLOBS_NAMI bool "Include blobs for nami audio." select NHLT_DA7219 - select NHLT_DMIC_4CH + select NHLT_DMIC_2CH select NHLT_MAX98357 config INCLUDE_NHLT_BLOBS_NOCTURNE bool "Include blobs for nocturne audio." - select NHLT_DMIC_4CH + select NHLT_DMIC_2CH select NHLT_MAX98373 config INCLUDE_NHLT_BLOBS_RAMMUS bool "Include blobs for rammus audio." select NHLT_DA7219 - select NHLT_DMIC_4CH + select NHLT_DMIC_2CH select NHLT_MAX98927 config MAINBOARD_DIR diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index a801e2b10e1..d149954ed14 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -37,7 +37,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/nhlt.c b/src/mainboard/google/poppy/variants/atlas/nhlt.c index ee642c0fc6f..b9b7c20ffb8 100644 --- a/src/mainboard/google/poppy/variants/atlas/nhlt.c +++ b/src/mainboard/google/poppy/variants/atlas/nhlt.c @@ -7,9 +7,9 @@ void variant_nhlt_init(struct nhlt *nhlt) { - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC arrays.\n"); /* Dialog DA7219 Headset codec. */ if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index b209fcdd7f1..84b3ebad746 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/nhlt.c b/src/mainboard/google/poppy/variants/baseboard/nhlt.c index b3ead3b3de9..c281096e95c 100644 --- a/src/mainboard/google/poppy/variants/baseboard/nhlt.c +++ b/src/mainboard/google/poppy/variants/baseboard/nhlt.c @@ -11,10 +11,6 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) if (nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); - /* Maxim MAX98927 Smart Amps for left and right channel */ /* Render time_slot is 0 and feedback time_slot is 2 */ if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0, 0, 2)) diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 2b1a19021c9..ed5a1180133 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -3,6 +3,15 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "1" @@ -28,7 +37,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index b703d40fc3c..5099a1e194c 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -174,6 +174,56 @@ const char *smbios_mainboard_manufacturer(void) return manuf; } +const char *smbios_mainboard_product_name(void) +{ + uint32_t sku_id = variant_board_sku(); + static char product[12]; + + switch (sku_id) { + case SKU_0_PANTHEON: + case SKU_1_PANTHEON: + case SKU_2_PANTHEON: + case SKU_3_PANTHEON: + case SKU_4_PANTHEON: + snprintf(product, sizeof(product), "Pantheon"); break; + case SKU_0_VAYNE: + case SKU_1_VAYNE: + case SKU_2_VAYNE: + snprintf(product, sizeof(product), "Vayne"); break; + case SKU_0_AKALI: + case SKU_1_AKALI: + snprintf(product, sizeof(product), "Akali"); break; + case SKU_0_AKALI360: + case SKU_1_AKALI360: + snprintf(product, sizeof(product), "Akali 360"); break; + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + snprintf(product, sizeof(product), "Bard"); break; + case SKU_0_EKKO: + case SKU_1_EKKO: + case SKU_2_EKKO: + case SKU_3_EKKO: + snprintf(product, sizeof(product), "Ekko"); break; + case SKU_0_SONA: + case SKU_1_SONA: + snprintf(product, sizeof(product), "Sona"); break; + case SKU_0_SYNDRA: + case SKU_1_SYNDRA: + case SKU_2_SYNDRA: + case SKU_3_SYNDRA: + case SKU_4_SYNDRA: + case SKU_5_SYNDRA: + case SKU_6_SYNDRA: + case SKU_7_SYNDRA: + snprintf(product, sizeof(product), "Syndra"); break; + default: + snprintf(product, sizeof(product), "Nami"); break; + } + return product; +} + const char *mainboard_vbt_filename(void) { uint32_t sku_id = variant_board_sku(); diff --git a/src/mainboard/google/poppy/variants/nami/nhlt.c b/src/mainboard/google/poppy/variants/nami/nhlt.c index 343b835c387..14c16a61814 100644 --- a/src/mainboard/google/poppy/variants/nami/nhlt.c +++ b/src/mainboard/google/poppy/variants/nami/nhlt.c @@ -7,9 +7,9 @@ void variant_nhlt_init(struct nhlt *nhlt) { - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); /* Dialog DA7219 Headset codec. */ if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index e8c735d30c6..ee0b55ff4b1 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -3,6 +3,15 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" @@ -28,7 +37,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl index ebc3c909e0d..0e87e19ccdd 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "ipu_mainboard.asl" -#include "ipu_endpoints.asl" -#include -#include "cam0.asl" +//#include "ipu_mainboard.asl" +//#include "ipu_endpoints.asl" +//#include +//#include "cam0.asl" diff --git a/src/mainboard/google/poppy/variants/nautilus/nhlt.c b/src/mainboard/google/poppy/variants/nautilus/nhlt.c index 267dbfc6bb6..a903a75b20c 100644 --- a/src/mainboard/google/poppy/variants/nautilus/nhlt.c +++ b/src/mainboard/google/poppy/variants/nautilus/nhlt.c @@ -7,9 +7,9 @@ void variant_nhlt_init(struct nhlt *nhlt) { - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); /* Dialog DA7219 Headset codec. */ if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index a193e6a52bf..eae612e610b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -30,7 +30,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl index 51b4ebc0460..86fdc2a4c84 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "ipu_mainboard.asl" -#include "ipu_endpoints.asl" -#include "cam0.asl" -#include "cam1.asl" +//#include "ipu_mainboard.asl" +//#include "ipu_endpoints.asl" +//#include "cam0.asl" +//#include "cam1.asl" diff --git a/src/mainboard/google/poppy/variants/nocturne/nhlt.c b/src/mainboard/google/poppy/variants/nocturne/nhlt.c index a3b239932c2..03a14f41287 100644 --- a/src/mainboard/google/poppy/variants/nocturne/nhlt.c +++ b/src/mainboard/google/poppy/variants/nocturne/nhlt.c @@ -7,9 +7,9 @@ void variant_nhlt_init(struct nhlt *nhlt) { - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); /* MAXIM Smart Amps for left and right speakers. */ /* Render time_slot is 0 and feedback time_slot is 2 */ diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index beb78c65d9f..7fcc3a16166 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -37,7 +37,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/nhlt.c b/src/mainboard/google/poppy/variants/rammus/nhlt.c index 14c6e708f79..938672f6b5e 100644 --- a/src/mainboard/google/poppy/variants/rammus/nhlt.c +++ b/src/mainboard/google/poppy/variants/rammus/nhlt.c @@ -7,9 +7,9 @@ void variant_nhlt_init(struct nhlt *nhlt) { - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); /* Dialog DA7219 Headset codec. */ if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) @@ -17,7 +17,7 @@ void variant_nhlt_init(struct nhlt *nhlt) /* Maxim MAX98927 Smart Amps for left and right channel */ /* Render time_slot is 0 and feedback time_slot is 2 */ - if (nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP0, 0, 2)) + if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0, 0, 2)) printk(BIOS_ERR, "Couldn't add Maxim MAX98927\n"); } diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index bcfb2668526..d4f45bfc791 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -3,6 +3,15 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" @@ -28,7 +37,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl index 318b0dea040..2b947038b77 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +//#include diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig index 1fe0de525a3..52175440512 100644 --- a/src/mainboard/google/puff/Kconfig +++ b/src/mainboard/google/puff/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 + select DRIVERS_AUDIO_SOF select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 @@ -175,7 +176,7 @@ config VBOOT select VBOOT_EARLY_EC_SYNC config USE_PM_ACPI_TIMER - default n + default y config EDK2_BOOT_TIMEOUT int diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 976d82970c8..4c8b2096203 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/cannonlake # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Enable DPTF register "dptf_enable" = "1" register "power_limits_config" = "{ @@ -347,7 +347,12 @@ chip soc/intel/cannonlake end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on + chip drivers/sof + register "jack_tplg" = "rt5682" + device generic 0 on end + end + end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index c40c61ca7e2..a5cf3baa678 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -388,6 +388,14 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[10]" = "1" end device pci 1e.3 off end # GSPI #1 + device pci 1f.3 on + chip drivers/sof + register "spkr_tplg" = "rt1015" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end # Intel HDA end # VR Settings Configuration for 4 Domains diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index bfbb66bf801..a419c0e4169 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -89,6 +89,11 @@ Scope (\_SB.PCI0.I2C2) { BOARD_CODEC_IRQ } + + GpioIo (Exclusive, PullNone, 0, 0, , "\\_SB.GPSC", 0, ResourceConsumer, ,){ 0x000E } + + GpioIo (Exclusive, PullNone, 0, 0, , "\\_SB.GPSC", 0, ResourceConsumer, ,){ 0x000F } + }) Method (_STA) @@ -106,14 +111,24 @@ Scope (\_SB.PCI0.LPEA) { Name (GBUF, ResourceTemplate () { + /* Jack Detect (index 0) */ - GpioInt (Level, ActiveHigh, Exclusive, PullNone,, - "\\_SB.GPSC") { 14 } + GpioIo (Exclusive, PullNone, 0, 0, , "\\_SB.GPSC", 0, ResourceConsumer, ,){ 0x000E } /* Mic Detect (index 1) */ - GpioInt (Level, ActiveHigh, Exclusive, PullNone,, - "\\_SB.GPSC") { 15 } + GpioIo (Exclusive, PullNone, 0, 0, , "\\_SB.GPSC", 0, ResourceConsumer, ,){ 0x000F } + + /* SST Wants This */ + GpioInt (Edge, ActiveHigh, Exclusive, PullNone, 0x0000, + "\\_SB.GPSS", 0x00, ResourceConsumer, ,) + { + 0x001C // Pin list + } }) + Method (_DIS, 0x0, NotSerialized) + { + //Add a dummy disable function + } } #include diff --git a/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl index 9c0fc6b5356..73e9612b499 100644 --- a/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl +++ b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl @@ -7,7 +7,6 @@ Scope (\_SB.PCI0.I2C6) Device (ATSA) { Name (_HID, "ATML0001") - Name (_CID, EisaId ("PNP0C0E")) Name (_DDN, "Atmel Touchscreen") Name (_UID, 5) Name (ISTP, 0) /* TouchScreen */ diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 63a1fc7885e..9cf8c045d3b 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -27,9 +27,6 @@ DefinitionBlock( #include #include } - - /* Dynamic Platform Thermal Framework */ - #include "acpi/dptf.asl" } #include diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 358a92f9679..5d73df939a0 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -66,6 +66,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + case ACPI_S4: case ACPI_S5: if (gnvs->s5u0 == 0) google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index fb026316503..87447a5c016 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -97,7 +97,7 @@ config UART_FOR_CONSOLE config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." - select NHLT_DMIC_4CH_16B + select NHLT_DMIC_2CH_16B select NHLT_DA7219 select NHLT_MAX98357 diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index ddb78a54fd2..93a0b5e489c 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -67,7 +67,7 @@ chip soc/intel/apollolake register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "0" # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -128,7 +128,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index d14033065ca..87ab89afa41 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -67,7 +67,7 @@ chip soc/intel/apollolake register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "0" # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -128,7 +128,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI @@ -242,8 +242,8 @@ chip soc/intel/apollolake device pci 17.2 off end # - I2C 6 device pci 17.3 off end # - I2C 7 device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 + device pci 18.1 off end # - UART 1 + device pci 18.2 off end # - UART 2 device pci 18.3 off end # - UART 3 device pci 19.0 on end # - SPI 0 device pci 19.1 off end # - SPI 1 diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index ee1e0f3d874..9fabec98f9f 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -67,7 +67,7 @@ chip soc/intel/apollolake register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "0" # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -137,7 +137,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index de2e920f4af..124d779fdff 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -64,7 +64,7 @@ chip soc/intel/apollolake register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "0" # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -124,7 +124,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 197c911226f..7583dbc79db 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -67,7 +67,7 @@ chip soc/intel/apollolake register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "0" # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -133,7 +133,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index a3225ca111c..05a5428f144 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/meteorlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 86b961d9336..0df0620a5e8 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,7 +27,7 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" register "dptf_enable" = "1" register "satapwroptimize" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 903bcc6d432..d26f8545349 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,7 +30,7 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" register "dptf_enable" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" diff --git a/src/mainboard/google/slippy/acpi/superio.asl b/src/mainboard/google/slippy/acpi/superio.asl index 587bb8bf0ff..4a1456bb0ed 100644 --- a/src/mainboard/google/slippy/acpi/superio.asl +++ b/src/mainboard/google/slippy/acpi/superio.asl @@ -6,7 +6,6 @@ #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources #define SIO_EC_HOST_ENABLE // EC Host Interface Resources #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 /* ACPI code for EC SuperIO functions */ #include diff --git a/src/mainboard/google/slippy/variants/peppy/gpio.c b/src/mainboard/google/slippy/variants/peppy/gpio.c index 2ed92cdb81c..e50e6cd56ad 100644 --- a/src/mainboard/google/slippy/variants/peppy/gpio.c +++ b/src/mainboard/google/slippy/variants/peppy/gpio.c @@ -22,7 +22,7 @@ const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { LP_GPIO_UNUSED, /* 16: UNUSED */ LP_GPIO_UNUSED, /* 17: UNUSED */ LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ - LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_NATIVE, /* 19: PCIE_CLKREQ_LTE# */ LP_GPIO_UNUSED, /* 20: UNUSED */ LP_GPIO_UNUSED, /* 21: UNUSED */ LP_GPIO_UNUSED, /* 22: UNUSED */ diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index a96ec197dd0..e22087424bc 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -142,4 +142,33 @@ Scope (\_SB.PCI0.I2C1) } } } + + Device (ALSI) + { + Name (_HID, "ISL29018") + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 6) + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_LIGHTSENSOR_IRQ + } + }) + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } } diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl index 4f312fa3ca3..ef4263037c6 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl @@ -85,6 +85,23 @@ Scope (\_SB.PCI0.XHCI.HUB7.PRT5) Return (GPLD (1)) } } +Scope (\_SB.PCI0.XHCI.HUB7.PRT6) +{ + // SIM USB 2.0 Slot + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} Scope (\_SB.PCI0.XHCI.HUB7.PRT7) { // SD Card diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index bb30f763f3a..75a70ee5cdb 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -23,6 +23,8 @@ chip northbridge/intel/haswell # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013c0000" end + + device pci 1c.1 on end # PCIe Port #2 end end end diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 32fdd97e947..2347690baba 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -43,8 +43,8 @@ const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { USB_PORT_MINI_PCIE }, { 0x0040, 1, 2, /* P4: Port B, CN6 */ USB_PORT_BACK_PANEL }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ - USB_PORT_SKIP }, + { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: SIM */ + USB_PORT_INTERNAL }, { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ USB_PORT_FLEX }, { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 51210e44ed4..5504b4ef128 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_AUDIO_SOF select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_GENESYSLOGIC_GL9763E @@ -26,6 +27,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS @@ -35,6 +37,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_TIGERLAKE + select SOC_INTEL_TIGERLAKE_S3 select TPM_GOOGLE_TI50 if BOARD_GOOGLE_VOLTEER2_TI50 select TPM_GOOGLE_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 @@ -51,11 +54,10 @@ config BOARD_GOOGLE_HALVOR config BOARD_GOOGLE_LINDAR select BOARD_GOOGLE_BASEBOARD_VOLTEER - select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_CALIB select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_I2C_RT1011 select INTEL_CAR_NEM - select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_MALEFOR select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 4193d3d1e7f..eeaf61379fe 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -28,6 +28,7 @@ DefinitionBlock( #include #include #include + #include #if CONFIG(VARIANT_HAS_MIPI_CAMERA) #include #endif diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 3a54d3b728f..200d1e127fe 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -259,7 +259,7 @@ chip soc/intel/tigerlake register "DdiPort4Ddc" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Enable DPTF register "dptf_enable" = "1" @@ -357,7 +357,9 @@ chip soc/intel/tigerlake register "FastPkgCRampDisable" = "1" device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref dptf on # Default DPTF Policy for all Volteer boards if not overridden chip drivers/intel/dptf @@ -521,5 +523,13 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98373" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 4b45bfc3f66..28f72d70d6e 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -271,6 +271,12 @@ chip soc/intel/tigerlake register "sdmode_delay" = "5" device generic 0 on end end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end device ref pcie_rp5 on end device ref pmc hidden diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index fe5f698c76b..6d2eaf006be 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -122,10 +122,15 @@ chip soc/intel/tigerlake end # DPTF device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 end - device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_dma0 on + probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 end diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 376296183ae..7bb91eacef5 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -147,7 +147,7 @@ chip soc/intel/tigerlake register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.reset_delay_ms" = "30" + register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" register "generic.enable_delay_ms" = "12" @@ -203,6 +203,12 @@ chip soc/intel/tigerlake register "sdmode_delay" = "5" device generic 0 on end end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm1" + device generic 0 on end + end end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 2ad6c0834a3..2152ec479ac 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -272,6 +272,12 @@ chip soc/intel/tigerlake register "sdmode_delay" = "5" device generic 0 on end end + chip drivers/sof + register "spkr_tplg" = "max98357a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end device ref pcie_rp5 on end device ref pmc hidden diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index b74bb238cd3..e543b9fd636 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -276,6 +276,12 @@ chip soc/intel/tigerlake probe AUDIO MAX98373_ALC5682I_I2S_UP4 probe AUDIO MAX98360_ALC5682I_I2S probe AUDIO RT1011_ALC5682I_I2S + chip drivers/sof + register "spkr_tplg" = "rt1011" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end end device ref pcie_rp9 on chip soc/intel/common/block/pcie/rtd3 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 68eb6ea5887..382c6b7c16f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -249,7 +249,7 @@ chip soc/amd/picasso device ref iommu on end device ref gpp_bridge_1 on # Wifi chip drivers/wifi/generic - register "wake" = "GEVENT_8" + #register "wake" = "GEVENT_8" device pci 00.0 on end end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 4bb42dea1c9..e2834aaab2e 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -247,7 +247,7 @@ chip soc/amd/picasso device ref iommu on end device ref gpp_bridge_1 on # Wifi chip drivers/wifi/generic - register "wake" = "GEVENT_8" + #register "wake" = "GEVENT_8" device pci 00.0 on end end end diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index 5c767aacc50..c73359cdf73 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -53,7 +53,6 @@ /* Enable LID switch */ #define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN EC_WAKE_GPI /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index e3a1f51f77d..3cb24e7d15b 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -47,7 +47,7 @@ chip soc/amd/picasso register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" # 32ms: Rise time of the reset line # 20ms: Firmware ready time @@ -59,7 +59,7 @@ chip soc/amd/picasso register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl index d9c9d614a73..972da693c3f 100644 --- a/src/mainboard/samsung/lumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl @@ -23,9 +23,9 @@ Scope (\_SB) { Device (TPAD) { - // Report as a Sleep Button device so - // Linux will automatically enable for wake - Name(_HID, EisaId("PNP0C0E")) + Name(_HID, "CYSM0000") + Name(_UID, 1) + Name(_HRV, 2) // Trackpad Wake is GPIO11 Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) @@ -33,7 +33,7 @@ Scope (\_SB) { Name(_CRS, ResourceTemplate() { // PIRQF -> GSI21 - Interrupt (ResourceConsumer, Edge, ActiveLow) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) { BOARD_TRACKPAD_IRQ } diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl index 1edaafd84e5..73cb3670f80 100644 --- a/src/mainboard/samsung/stumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl @@ -102,11 +102,7 @@ Scope (\_TZ) } Method (_AC4) { - If (\FLVL <= 4) { - Return (CTOK (\F4OF)) - } Else { - Return (CTOK (\F4ON)) - } + Return (CTOK (0)) } Name (_AL0, Package () { FAN0 }) diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 6912ca1a76e..bf297d7cf3b 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -19,8 +19,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 1; gnvs->s5u1 = 1; - gnvs->f4of = FAN4_THRESHOLD_OFF; - gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; gnvs->f3of = FAN3_THRESHOLD_OFF; diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index b348f140cc6..c1c11b357fd 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -74,6 +74,8 @@ chip northbridge/intel/sandybridge register "peci_tmpin" = "3" # Enable FAN3 register "fan3_enable" = "true" + # Default FAN3 speed + register "fan3_speed" = "0x90" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/samsung/stumpy/thermal.h b/src/mainboard/samsung/stumpy/thermal.h index fa8a08ed75d..41327e19bcf 100644 --- a/src/mainboard/samsung/stumpy/thermal.h +++ b/src/mainboard/samsung/stumpy/thermal.h @@ -3,25 +3,23 @@ #ifndef STUMPY_THERMAL_H #define STUMPY_THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x90 /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 48 #define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 +#define FAN3_PWM 0xA0 /* Fan is at MEDIUM speed */ #define FAN2_THRESHOLD_OFF 52 #define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 +#define FAN2_PWM 0xB0 /* Fan is at HIGH speed */ #define FAN1_THRESHOLD_OFF 60 #define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 +#define FAN1_PWM 0xC0 /* Fan is at FULL speed */ #define FAN0_THRESHOLD_OFF 66 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 6e6948b70f3..48a75ba15c2 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -400,20 +400,6 @@ static void gma_pm_init_post_vbios(struct device *dev) gtt_write(0x0a188, 0x00000001); } -/* Enable SCI to ACPI _GPE._L06 */ -static void gma_enable_swsci(void) -{ - u16 reg16; - - /* Clear DMISCI status */ - reg16 = inw(get_pmbase() + TCO1_STS); - reg16 &= DMISCI_STS; - outw(reg16, get_pmbase() + TCO1_STS); - - /* Clear and enable ACPI TCO SCI */ - enable_tco_sci(); -} - static void gma_func0_init(struct device *dev) { int lightup_ok = 0; @@ -450,8 +436,6 @@ static void gma_func0_init(struct device *dev) printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); gma_pm_init_post_vbios(dev); - - gma_enable_swsci(); } static void gma_generate_ssdt(const struct device *dev) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index cf1d61ce9fe..980a31babf4 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -49,3 +49,12 @@ Device (PDRC) /* Integrated graphics 0:2.0 */ #include + +Device (DPTF) +{ + Name (_ADR, 0x00040000) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } +} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index e35251359ac..d1642d5a23a 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -87,7 +87,7 @@ static void sandybridge_setup_graphics(void) printk(BIOS_DEBUG, "Initializing Graphics...\n"); /* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */ - gfxsize = get_uint_option("gfx_uma_size", 0); + gfxsize = get_uint_option("gfx_uma_size", 2); reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 3eed5cc9bc8..94be6985311 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -562,25 +562,6 @@ static void gma_pm_init_post_vbios(struct device *dev) } } -/* Enable SCI to ACPI _GPE._L06 */ -static void gma_enable_swsci(void) -{ - u16 reg16; - - /* Clear DMISCI status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); - reg16 &= DMISCI_STS; - outw(reg16, DEFAULT_PMBASE + TCO1_STS); - - /* Clear ACPI TCO status */ - outl(TCOSCI_STS, DEFAULT_PMBASE + GPE0_STS); - - /* Enable ACPI TCO SCIs */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(reg16, DEFAULT_PMBASE + GPE0_EN); -} - static void gma_func0_init(struct device *dev) { intel_gma_init_igd_opregion(); @@ -615,8 +596,6 @@ static void gma_func0_init(struct device *dev) gfx_set_init_done(1); } } - - gma_enable_swsci(); } static void gma_generate_ssdt(const struct device *device) diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 7ed622541f6..c47b7b78429 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -15,7 +15,7 @@ Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ Method(_STA, 0, NotSerialized) { - Return(0x0B) /* Status is visible */ + Return(0x0F) /* Status is visible */ } Method(_PRT,0, NotSerialized) diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl index e905c9738c2..13885344320 100644 --- a/src/soc/amd/stoneyridge/acpi/pci_int.asl +++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl @@ -30,77 +30,6 @@ P92E, 1, /* Port92 decode enable */ } - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12c), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1a0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1a8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1ac), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1b0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22c), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2a0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2a8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2aC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2b0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - Name(IRQB, ResourceTemplate(){ IRQ(Level,ActiveLow,Shared){15} }) diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 6a7ed2ea429..39cac3d4efc 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -99,17 +99,16 @@ Method(_CRS, 0) { CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* - * Declare memory between TOM1 and 4GB as available + * Declare memory between TOM1 and 0xFED40000 as available * for PCI MMIO. * Use ShiftLeft to avoid 64bit constant (for XP). * This will work even if the OS does 32bit arithmetic, as * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - MM1B = TOM1 - Local0 = 0x10000000 << 4 - Local0 -= TOM1 - MM1L = Local0 + Store(TOM1, MM1B) + Subtract(0xFED40000, TOM1, Local0) + Store(Local0, MM1L) Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0561d747f29..b96c03991fa 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_INTEL_TME select CPU_SUPPORTS_PM_TIMER_EMULATION + select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS select DISPLAY_FSP_VERSION_INFO select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 @@ -226,7 +227,7 @@ config PCIEXP_HOTPLUG_MEM config PCIEXP_HOTPLUG_PREFETCH_MEM hex - default 0x1c000000 + default 0x100000000 endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -438,9 +439,6 @@ config ACPI_ADL_IPU_ES_SUPPORT help Enables ACPI entry to provide silicon type information to IPU kernel driver. -config CHROMEOS - select DEFAULT_SOFTWARE_CONNECTION_MANAGER - config ALDERLAKE_ENABLE_SOC_WORKAROUND bool default y diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 9edaf771109..e4525f8a44e 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -327,7 +327,7 @@ Scope (_GPE) } } -Scope (\_SB.PCI0) +Scope (\_SB) { Device (IOM) { @@ -338,9 +338,12 @@ Scope (\_SB.PCI0) Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) /* Hide the device so that Windows does not complain on missing driver */ - Name (_STA, 0xB) + Name (_STA, 0xF) } +} +Scope (\_SB.PCI0) +{ /* * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR. diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index c28ee2d0a44..ada0caa01a3 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -109,7 +109,7 @@ static void soc_pmc_fill_ssdt(const struct device *dev) acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller"); /* Hide the device so that Windows does not complain on missing driver */ - acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 395d7aa6883..c026ec91cf0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -191,13 +191,18 @@ config VERSTAGE_ADDR The base address (in CAR) where verstage should be linked config FSP_HEADER_PATH - default "src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0" if VENDOR_GOOGLE && SOC_INTEL_GEMINILAKE default "src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1" if SOC_INTEL_GEMINILAKE default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" config FSP_FD_PATH default "3rdparty/fsp/ApolloLakeFspBinPkg/FspBin/Fsp.fd" +config FSP_M_FILE + default "3rdparty/blobs/soc/intel/glk/fsp/release/Fsp_M.fd" if SOC_INTEL_GEMINILAKE + +config FSP_S_FILE + default "3rdparty/blobs/soc/intel/glk/fsp/release/Fsp_S.fd" if SOC_INTEL_GEMINILAKE + config FSP_M_ADDR hex default 0xfef40000 diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl index f7cf04f3133..eb800c3c0f2 100644 --- a/src/soc/intel/apollolake/acpi/pcie.asl +++ b/src/soc/intel/apollolake/acpi/pcie.asl @@ -7,7 +7,7 @@ Device (RP01) Name (_ADR, 0x00140000) Name (_DDN, "PCIe-B 0") - #include "pcie_port.asl" +// #include "pcie_port.asl" } Device (RP03) @@ -15,5 +15,5 @@ Device (RP03) Name (_ADR, 0x00130000) Name (_DDN, "PCIe-A 0") - #include "pcie_port.asl" +// #include "pcie_port.asl" } diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index d90b42ea82d..55585c4dd95 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -42,5 +42,9 @@ scope (\_SB) { Return (^RBUF) } + Method (_STA, 0x0, NotSerialized) + { + Return(0xb) + } } } diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index dacdd29e066..6ab8db4763f 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -241,6 +241,15 @@ Device (IOSF) RBAS = CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xD0 Return (^RBUF) } + + Method (_STA) + { +#if CONFIG(CHROMEOS) + Return (0xF) +#else + Return (0x0) +#endif + } } /* LPC Bridge 0:1f.0 */ diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 8892b531f98..9da82aafd6b 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -70,15 +70,6 @@ void baytrail_init_scc(void) void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { - struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR16(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, - SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), - REG_SCRIPT_END - }; struct resource *bar; struct device_nvs *dev_nvs = acpi_get_device_nvs(); @@ -93,7 +84,4 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) /* Device is enabled in ACPI mode */ dev_nvs->scc_en[nvs_index] = 1; - - /* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); } diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 9a478437fda..d5272b9ced2 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -95,10 +95,10 @@ static void southbridge_smi_sleep(void) wbinvd(); break; case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, (slp_typ == ACPI_S4) ? + "SMI#: Entering S4 (Suspend-To-Disk)\n" : + "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ disable_all_gpe(); @@ -204,14 +204,6 @@ static void soc_legacy(void) struct device_nvs *dev_nvs = acpi_get_device_nvs(); u32 reg32; - /* LPE Device */ - if (dev_nvs->lpe_en) { - reg32 = iosf_port58_read(LPE_PCICFGCTR1); - reg32 &= - ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN); - iosf_port58_write(LPE_PCICFGCTR1, reg32); - } - /* SCC Devices */ #define SCC_ACPI_MODE_DISABLE(name_) \ do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \ @@ -223,29 +215,30 @@ static void soc_legacy(void) SCC_ACPI_MODE_DISABLE(MMC); SCC_ACPI_MODE_DISABLE(SD); SCC_ACPI_MODE_DISABLE(SDIO); +} - /* LPSS Devices */ -#define LPSS_ACPI_MODE_DISABLE(name_) \ - do { if (dev_nvs->lpss_en[LPSS_NVS_ ## name_]) { \ - reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \ - reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \ - iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \ +/* + * soc_end_of_dxe: A payload (Tianocore) has indicated that the + * UEFI payload is being loaded. Switch SCC devices that are + * in PCI mode to ACPI mode so that Windows will work. + * + */ +static void soc_end_of_dxe(void) +{ + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + u32 reg32; + + /* SCC Devices */ +#define SCC_ACPI_MODE_ENABLE(name_) \ + do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \ + reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ + reg32 |= (SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \ + iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ } } while (0) - LPSS_ACPI_MODE_DISABLE(SIO_DMA1); - LPSS_ACPI_MODE_DISABLE(I2C1); - LPSS_ACPI_MODE_DISABLE(I2C2); - LPSS_ACPI_MODE_DISABLE(I2C3); - LPSS_ACPI_MODE_DISABLE(I2C4); - LPSS_ACPI_MODE_DISABLE(I2C5); - LPSS_ACPI_MODE_DISABLE(I2C6); - LPSS_ACPI_MODE_DISABLE(I2C7); - LPSS_ACPI_MODE_DISABLE(SIO_DMA2); - LPSS_ACPI_MODE_DISABLE(PWM1); - LPSS_ACPI_MODE_DISABLE(PWM2); - LPSS_ACPI_MODE_DISABLE(HSUART1); - LPSS_ACPI_MODE_DISABLE(HSUART2); - LPSS_ACPI_MODE_DISABLE(SPI); + SCC_ACPI_MODE_ENABLE(MMC); + SCC_ACPI_MODE_ENABLE(SD); + SCC_ACPI_MODE_ENABLE(SDIO); } static void southbridge_smi_store(void) @@ -290,6 +283,10 @@ static void southbridge_smi_apmc(void) if (CONFIG(SMMSTORE)) southbridge_smi_store(); break; + case APM_CNT_END_OF_DXE: + soc_end_of_dxe(); + break; + } mainboard_smi_apmc(reg8); diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 3dcc6c19511..de1ddab2e54 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -240,6 +240,15 @@ Device (IOSF) RBAS = CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xD0 Return (^RBUF) } + + Method (_STA) + { +#if CONFIG(CHROMEOS) + Return (0xF) +#else + Return (0x0) +#endif + } } /* LPC Bridge 0:1f.0 */ diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index f34eb6448f2..394f042305e 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -119,10 +119,10 @@ static void southbridge_smi_sleep(void) wbinvd(); break; case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, (slp_typ == ACPI_S4) ? + "SMI#: Entering S4 (Suspend-To-Disk)\n" : + "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ disable_all_gpe(); diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 5a80d32191f..ac3af30274c 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -69,7 +69,7 @@ config CONSOLE_UART_BASE_ADDRESS config DISABLE_ME_PCI bool "Disable Intel ME PCI interface (MEI1)" - default y + default n help Disable and hide the ME PCI interface during finalize stage of boot. This will prevent the OS (and userspace apps) from interacting with diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 14d08af7af8..5dcaad6dc7b 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -167,10 +167,10 @@ static void southbridge_smi_sleep(void) wbinvd(); break; case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, (slp_typ == ACPI_S4) ? + "SMI#: Entering S4 (Suspend-To-Disk)\n" : + "SMI#: Entering S5 (Soft Power off)\n"); /* Turn off backlight if needed */ backlight_off(); diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index 42613a8f84f..7bd499ee055 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -5,8 +5,7 @@ config SOC_INTEL_COMMON_BLOCK_TIMER config USE_LEGACY_8254_TIMER bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS || VGA_ROM_RUN - default n + default y help Setting this makes the Legacy 8254 Timer available by disabling clock gating. This needs to be enabled in order to boot a legacy diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 4ae21b87e49..ac8d17e3799 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -218,4 +218,16 @@ config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1400 + +config INTEL_GMA_BCLV_OFFSET + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 endif diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 44d09080ea4..27a45c210e8 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c +ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 896a79a0f90..e45e6861225 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include +#include #include #include #include @@ -432,6 +433,9 @@ struct soc_intel_jasperlake_config { * false: Disabled (more wakes, higher power) */ bool cnvi_reduce_s0ix_pwr_usage; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c new file mode 100644 index 00000000000..773f3c6de8b --- /dev/null +++ b/src/soc/intel/jasperlake/graphics.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *const dev) +{ + const struct soc_intel_jasperlake_config *const chip = dev->chip_info; + return &chip->gfx; +} diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index b84cc552b8f..ee807a59800 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_INTEL_TME select CPU_SUPPORTS_PM_TIMER_EMULATION + select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS select DEFAULT_X2APIC_LATE_WORKAROUND select DISPLAY_FSP_VERSION_INFO_2 select DRIVERS_USB_ACPI @@ -333,9 +334,6 @@ config MRC_CHANNEL_WIDTH int default 16 -config CHROMEOS - select DEFAULT_SOFTWARE_CONNECTION_MANAGER - config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET hex default 0x800000 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 0e7bb64a800..32920f6f890 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_INTEL_TME select CPU_SUPPORTS_PM_TIMER_EMULATION + select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS select DISPLAY_FSP_VERSION_INFO if !FSP_TYPE_IOT select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 @@ -295,9 +296,6 @@ config MRC_CHANNEL_WIDTH int default 16 -config CHROMEOS - select DEFAULT_SOFTWARE_CONNECTION_MANAGER - # Intel recommends reserving the following resources per USB4 root port, # from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5 # - 42 buses @@ -312,7 +310,7 @@ config PCIEXP_HOTPLUG_MEM default 0xc200000 # 194 MiB config PCIEXP_HOTPLUG_PREFETCH_MEM - default 0x1c000000 # 448 MiB + default 0x100000000 # 4GiB endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 08b348062f3..7a95b3e5f48 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -327,7 +327,7 @@ Scope (_GPE) } } -Scope (\_SB.PCI0) +Scope (\_SB) { Device (IOM) { @@ -338,9 +338,11 @@ Scope (\_SB.PCI0) Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) /* Hide the device so that Windows does not complain on missing driver */ - Name (_STA, 0xB) + Name (_STA, 0xF) } - +} +Scope (\_SB.PCI0) +{ /* * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR. diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 5ad8a8976ab..770264705e2 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -108,7 +108,7 @@ static void soc_pmc_fill_ssdt(const struct device *dev) acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller"); /* Hide the device so that Windows does not complain on missing driver */ - acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 66c7dd2997b..caf485412a7 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -192,7 +192,6 @@ static void intel_me_init(struct device *dev) #if CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: #endif - intel_me_hide(dev); break; case ME_NORMAL_BIOS_PATH: diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 2a6caa67db4..15510ff65d4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -191,7 +191,6 @@ static void intel_me_init(struct device *dev) #if CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: #endif - intel_me_hide(dev); break; case ME_NORMAL_BIOS_PATH: diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 3c190757d66..4f560f45757 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -24,6 +24,17 @@ static void pch_smbus_init(struct device *dev) smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } +static void smbus_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) +{ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((0x04B4 & 0xffff) << 16) | (0x18D1 & 0xffff)); +} + +static struct pci_operations smbus_pci_ops = { + .set_subsystem = smbus_set_subsystem, +}; + static const char *smbus_acpi_name(const struct device *dev) { return "SBUS"; @@ -36,7 +47,7 @@ static struct device_operations smbus_ops = { .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &smbus_pci_ops, .acpi_name = smbus_acpi_name, }; diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 63058124a56..c58809c6dfe 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -86,7 +86,7 @@ config CONSOLE_UART_BASE_ADDRESS config DISABLE_ME_PCI bool "Disable Intel ME PCI interface (MEI1)" - default y + default n help Disable and hide the ME PCI interface during finalize stage of boot. This will prevent the OS (and userspace apps) from interacting with diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8caafb716fd..1b05a49396a 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -119,10 +119,10 @@ static void southbridge_smi_sleep(void) wbinvd(); break; case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, (slp_typ == ACPI_S4) ? + "SMI#: Entering S4 (Suspend-To-Disk)\n" : + "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ disable_all_gpe(); diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 1219bccf8c7..9a8935a479e 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -273,56 +273,21 @@ static void usb_xhci_clock_gating(struct device *dev) static void usb_xhci_init(struct device *dev) { + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); u32 reg32; - u8 *mem_base = usb_xhci_mem_base(dev); struct southbridge_intel_lynxpoint_config *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); + /* Disable Compliance Mode Entry */ + reg32 = read32(res2mmio(res, 0x80ec, 0)); + reg32 |= (1 << 0); + write32(res2mmio(res, 0x80ec, 0), reg32); + /* Enable clock gating first */ usb_xhci_clock_gating(dev); - reg32 = read32(mem_base + 0x8144); - if (pch_is_lp()) { - /* XHCIBAR + 8144h[8,7,6] = 111b */ - reg32 |= (1 << 8) | (1 << 7) | (1 << 6); - } else { - /* XHCIBAR + 8144h[8,7,6] = 100b */ - reg32 &= ~((1 << 7) | (1 << 6)); - reg32 |= (1 << 8); - } - write32(mem_base + 0x8144, reg32); - - if (pch_is_lp()) { - /* XHCIBAR + 816Ch[19:0] = 000e0038h */ - reg32 = read32(mem_base + 0x816c); - reg32 &= ~0x000fffff; - reg32 |= 0x000e0038; - write32(mem_base + 0x816c, reg32); - - /* D20:F0:B0h[17,14,13] = 100b */ - pci_update_config32(dev, 0xb0, ~((1 << 14) | (1 << 13)), 1 << 17); - } - - reg32 = pci_read_config32(dev, 0x50); - if (pch_is_lp()) { - /* D20:F0:50h[28:0] = 0FCE2E5Fh */ - reg32 &= ~0x1fffffff; - reg32 |= 0x0fce2e5f; - } else { - /* D20:F0:50h[26:0] = 07886E9Fh */ - reg32 &= ~0x07ffffff; - reg32 |= 0x07886e9f; - } - pci_write_config32(dev, 0x50, reg32); - - /* D20:F0:44h[31] = 1 (Access Control Bit) */ - pci_or_config32(dev, 0x44, 1 << 31); - - /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ - pci_update_config32(dev, 0x40, ~(1 << 23), 1 << 31); /* unsupported request */ - if (acpi_is_wakeup_s3()) { /* Reset ports that are disabled or * polling before returning to the OS. */ diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl index 117de961db9..3e1a9d38ca0 100644 --- a/src/superio/smsc/mec1308/acpi/superio.asl +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -3,7 +3,8 @@ // Scope is \_SB.PCI0.LPCB Device (SIO) { - Name (_ADR, 0x2E) + Name (_HID, EisaId ("PNP0A05")) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) Field (SIOA, ByteAcc, NoLock, Preserve) { diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig index 60c0c228a79..87564e8d138 100644 --- a/src/vendorcode/google/Kconfig +++ b/src/vendorcode/google/Kconfig @@ -9,3 +9,22 @@ config GOOGLE_SMBIOS_MAINBOARD_VERSION help Provide a common implementation for mainboard version, which returns a formatted 'rev%d' board_id() string. + +config CHROMEOS_DSM_CALIB + bool + default n + depends on VPD + help + On some boards, there are calibrated parameters for Dynamic Speaker Management(DSM) + stored in VPD. Enable this config to read and parse these VPD values and write them + to ACPI DSD table in device driver. These parameters will be applied by kernel driver + through device property at boot. + +config CHROMEOS_DSM_PARAM_FILE_NAME + bool + default n + depends on CHROMEOS_DSM_CALIB + help + On some boards, there are different dsm parameter files for Dynamic Speaker + Management (DSM). Enable this config to assign dsm parameters file name in ACPI + SSDT table. Kernel driver uses this to load the DSM parameter file. diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc index c67ea20268e..8479feb9ee0 100644 --- a/src/vendorcode/google/Makefile.inc +++ b/src/vendorcode/google/Makefile.inc @@ -2,4 +2,5 @@ subdirs-$(CONFIG_CHROMEOS) += chromeos +ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION) += smbios.c diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 868492062ea..00c4f1f5052 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -57,23 +57,6 @@ config CHROMEOS_USE_EC_WATCHDOG_FLAG help Use the AP watchdog flag stored in EC. -config CHROMEOS_DSM_CALIB - bool - default n - help - On some boards, there are calibrated parameters for Dynamic Speaker Management(DSM) - stored in VPD. Enable this config to read and parse these VPD values and write them - to ACPI DSD table in device driver. These parameters will be applied by kernel driver - through device property at boot. - -config CHROMEOS_DSM_PARAM_FILE_NAME - bool - default n - help - On some boards, there are different dsm parameter files for Dynamic Speaker - Management (DSM). Enable this config to assign dsm parameters file name in ACPI - SSDT table. Kernel driver uses this to load the DSM parameter file. - config CHROMEOS_CSE_BOARD_RESET_OVERRIDE bool default n @@ -97,4 +80,5 @@ config CHROMEOS_NVS depends on ACPI_SOC_NVS endif # CHROMEOS + endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index ce77194070b..fbfd7a4e2fd 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -8,7 +8,6 @@ ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c -ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_GOOGLE) += cr50_enable_update.c romstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c diff --git a/src/vendorcode/google/chromeos/dsm_calib.c b/src/vendorcode/google/dsm_calib.c similarity index 100% rename from src/vendorcode/google/chromeos/dsm_calib.c rename to src/vendorcode/google/dsm_calib.c