diff --git a/ARM/gcc_clang/def/R7FA4L1BB3CAG.json b/ARM/gcc_clang/def/R7FA4L1BB3CAG.json index f20b5f97ed..5db3456947 100644 --- a/ARM/gcc_clang/def/R7FA4L1BB3CAG.json +++ b/ARM/gcc_clang/def/R7FA4L1BB3CAG.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BB3CAH.json b/ARM/gcc_clang/def/R7FA4L1BB3CAH.json index 001e731878..82d8cdfc71 100644 --- a/ARM/gcc_clang/def/R7FA4L1BB3CAH.json +++ b/ARM/gcc_clang/def/R7FA4L1BB3CAH.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BB4CFL.json b/ARM/gcc_clang/def/R7FA4L1BB4CFL.json index 44ab33a884..1874eae385 100644 --- a/ARM/gcc_clang/def/R7FA4L1BB4CFL.json +++ b/ARM/gcc_clang/def/R7FA4L1BB4CFL.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BB4CFM.json b/ARM/gcc_clang/def/R7FA4L1BB4CFM.json index 1d551d5786..afa43f0fa0 100644 --- a/ARM/gcc_clang/def/R7FA4L1BB4CFM.json +++ b/ARM/gcc_clang/def/R7FA4L1BB4CFM.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BB4CFP.json b/ARM/gcc_clang/def/R7FA4L1BB4CFP.json index 5ab1ec578b..2584e8abc5 100644 --- a/ARM/gcc_clang/def/R7FA4L1BB4CFP.json +++ b/ARM/gcc_clang/def/R7FA4L1BB4CFP.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BB4CNE.json b/ARM/gcc_clang/def/R7FA4L1BB4CNE.json index 921721b98a..8ae86e0c4d 100644 --- a/ARM/gcc_clang/def/R7FA4L1BB4CNE.json +++ b/ARM/gcc_clang/def/R7FA4L1BB4CNE.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BD3CAG.json b/ARM/gcc_clang/def/R7FA4L1BD3CAG.json index 36e2b65c86..dce43bbc08 100644 --- a/ARM/gcc_clang/def/R7FA4L1BD3CAG.json +++ b/ARM/gcc_clang/def/R7FA4L1BD3CAG.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BD3CAH.json b/ARM/gcc_clang/def/R7FA4L1BD3CAH.json index 4eb812c091..dbe4268954 100644 --- a/ARM/gcc_clang/def/R7FA4L1BD3CAH.json +++ b/ARM/gcc_clang/def/R7FA4L1BD3CAH.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BD4CFL.json b/ARM/gcc_clang/def/R7FA4L1BD4CFL.json index 57e6ce127f..9e763a08db 100644 --- a/ARM/gcc_clang/def/R7FA4L1BD4CFL.json +++ b/ARM/gcc_clang/def/R7FA4L1BD4CFL.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BD4CFM.json b/ARM/gcc_clang/def/R7FA4L1BD4CFM.json index d422a5f829..2b21ec4cb3 100644 --- a/ARM/gcc_clang/def/R7FA4L1BD4CFM.json +++ b/ARM/gcc_clang/def/R7FA4L1BD4CFM.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BD4CFP.json b/ARM/gcc_clang/def/R7FA4L1BD4CFP.json index 619b69f179..06450eb641 100644 --- a/ARM/gcc_clang/def/R7FA4L1BD4CFP.json +++ b/ARM/gcc_clang/def/R7FA4L1BD4CFP.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4L1BD4CNE.json b/ARM/gcc_clang/def/R7FA4L1BD4CNE.json index 20b0d5e6dc..165a6f9ca7 100644 --- a/ARM/gcc_clang/def/R7FA4L1BD4CNE.json +++ b/ARM/gcc_clang/def/R7FA4L1BD4CNE.json @@ -451,36 +451,6 @@ "unused": "000000fe", "label": "Pll control register" }, - { - "address": "4001e031", - "default": "0", - "fields": [ - { - "hidden": false, - "init": "0", - "key": "MEMWAIT", - "label": "Memory Wait Cycle Select for Code Flash", - "mask": "3", - "settings": [ - { - "label": "No wait", - "value": "0" - }, - { - "label": "One wait", - "value": "1" - }, - { - "label": "Two waits", - "value": "2" - } - ] - } - ], - "key": "SYSTEM_MEMWAIT", - "unused": "000000fc", - "label": "Memory wait cycle control register for code flash" - }, { "address": "4001e032", "default": "1", diff --git a/ARM/gcc_clang/def/R7FA4M2AB3CFL.json b/ARM/gcc_clang/def/R7FA4M2AB3CFL.json index d0b115910f..51250f0485 100644 --- a/ARM/gcc_clang/def/R7FA4M2AB3CFL.json +++ b/ARM/gcc_clang/def/R7FA4M2AB3CFL.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AB3CFM.json b/ARM/gcc_clang/def/R7FA4M2AB3CFM.json index 7088561b48..555173948a 100644 --- a/ARM/gcc_clang/def/R7FA4M2AB3CFM.json +++ b/ARM/gcc_clang/def/R7FA4M2AB3CFM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AB3CFP.json b/ARM/gcc_clang/def/R7FA4M2AB3CFP.json index ded9f71387..186f5f7e99 100644 --- a/ARM/gcc_clang/def/R7FA4M2AB3CFP.json +++ b/ARM/gcc_clang/def/R7FA4M2AB3CFP.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AB3CNE.json b/ARM/gcc_clang/def/R7FA4M2AB3CNE.json index cad724c742..801d2bc015 100644 --- a/ARM/gcc_clang/def/R7FA4M2AB3CNE.json +++ b/ARM/gcc_clang/def/R7FA4M2AB3CNE.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AC3CFL.json b/ARM/gcc_clang/def/R7FA4M2AC3CFL.json index cb304944e5..27f634427f 100644 --- a/ARM/gcc_clang/def/R7FA4M2AC3CFL.json +++ b/ARM/gcc_clang/def/R7FA4M2AC3CFL.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AC3CFM.json b/ARM/gcc_clang/def/R7FA4M2AC3CFM.json index ccaeb2bdb5..8da6b979bd 100644 --- a/ARM/gcc_clang/def/R7FA4M2AC3CFM.json +++ b/ARM/gcc_clang/def/R7FA4M2AC3CFM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AC3CFP.json b/ARM/gcc_clang/def/R7FA4M2AC3CFP.json index 58487294fe..331c7fb044 100644 --- a/ARM/gcc_clang/def/R7FA4M2AC3CFP.json +++ b/ARM/gcc_clang/def/R7FA4M2AC3CFP.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AC3CNE.json b/ARM/gcc_clang/def/R7FA4M2AC3CNE.json index 2a5a693ba6..021f9075d6 100644 --- a/ARM/gcc_clang/def/R7FA4M2AC3CNE.json +++ b/ARM/gcc_clang/def/R7FA4M2AC3CNE.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AD3CFL.json b/ARM/gcc_clang/def/R7FA4M2AD3CFL.json index 7efe43c75a..00e3ac7d2f 100644 --- a/ARM/gcc_clang/def/R7FA4M2AD3CFL.json +++ b/ARM/gcc_clang/def/R7FA4M2AD3CFL.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AD3CFM.json b/ARM/gcc_clang/def/R7FA4M2AD3CFM.json index 9e3ce5e309..230a71aea5 100644 --- a/ARM/gcc_clang/def/R7FA4M2AD3CFM.json +++ b/ARM/gcc_clang/def/R7FA4M2AD3CFM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AD3CFP.json b/ARM/gcc_clang/def/R7FA4M2AD3CFP.json index fa7064d73d..767ace19c7 100644 --- a/ARM/gcc_clang/def/R7FA4M2AD3CFP.json +++ b/ARM/gcc_clang/def/R7FA4M2AD3CFP.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M2AD3CNE.json b/ARM/gcc_clang/def/R7FA4M2AD3CNE.json index 1257426d61..786bfdef56 100644 --- a/ARM/gcc_clang/def/R7FA4M2AD3CNE.json +++ b/ARM/gcc_clang/def/R7FA4M2AD3CNE.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AD2CBM.json b/ARM/gcc_clang/def/R7FA4M3AD2CBM.json index cf3d6f6c5f..3043db482f 100644 --- a/ARM/gcc_clang/def/R7FA4M3AD2CBM.json +++ b/ARM/gcc_clang/def/R7FA4M3AD2CBM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AD2CBQ.json b/ARM/gcc_clang/def/R7FA4M3AD2CBQ.json index 19fe4e4d8a..1eed25f083 100644 --- a/ARM/gcc_clang/def/R7FA4M3AD2CBQ.json +++ b/ARM/gcc_clang/def/R7FA4M3AD2CBQ.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AD3CBM.json b/ARM/gcc_clang/def/R7FA4M3AD3CBM.json index 572315f063..9e920588c9 100644 --- a/ARM/gcc_clang/def/R7FA4M3AD3CBM.json +++ b/ARM/gcc_clang/def/R7FA4M3AD3CBM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AD3CBQ.json b/ARM/gcc_clang/def/R7FA4M3AD3CBQ.json index f77b741a77..16bb89f87e 100644 --- a/ARM/gcc_clang/def/R7FA4M3AD3CBQ.json +++ b/ARM/gcc_clang/def/R7FA4M3AD3CBQ.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AD3CFB.json b/ARM/gcc_clang/def/R7FA4M3AD3CFB.json index 6139d5aea5..fff6a2ad94 100644 --- a/ARM/gcc_clang/def/R7FA4M3AD3CFB.json +++ b/ARM/gcc_clang/def/R7FA4M3AD3CFB.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AE2CBM.json b/ARM/gcc_clang/def/R7FA4M3AE2CBM.json index f7531fee61..9b937f440a 100644 --- a/ARM/gcc_clang/def/R7FA4M3AE2CBM.json +++ b/ARM/gcc_clang/def/R7FA4M3AE2CBM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AE2CBQ.json b/ARM/gcc_clang/def/R7FA4M3AE2CBQ.json index 64ac4e580d..1152a59b55 100644 --- a/ARM/gcc_clang/def/R7FA4M3AE2CBQ.json +++ b/ARM/gcc_clang/def/R7FA4M3AE2CBQ.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AE3CBM.json b/ARM/gcc_clang/def/R7FA4M3AE3CBM.json index 0c7eeebe19..139cfb73c4 100644 --- a/ARM/gcc_clang/def/R7FA4M3AE3CBM.json +++ b/ARM/gcc_clang/def/R7FA4M3AE3CBM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AE3CBQ.json b/ARM/gcc_clang/def/R7FA4M3AE3CBQ.json index e11b2392c3..87a6ab24d0 100644 --- a/ARM/gcc_clang/def/R7FA4M3AE3CBQ.json +++ b/ARM/gcc_clang/def/R7FA4M3AE3CBQ.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AE3CFB.json b/ARM/gcc_clang/def/R7FA4M3AE3CFB.json index 3e90d3c4e8..fc0c34ebf8 100644 --- a/ARM/gcc_clang/def/R7FA4M3AE3CFB.json +++ b/ARM/gcc_clang/def/R7FA4M3AE3CFB.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AE3CFM.json b/ARM/gcc_clang/def/R7FA4M3AE3CFM.json index 954923b7d1..e07b38ba8e 100644 --- a/ARM/gcc_clang/def/R7FA4M3AE3CFM.json +++ b/ARM/gcc_clang/def/R7FA4M3AE3CFM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AE3CFP.json b/ARM/gcc_clang/def/R7FA4M3AE3CFP.json index edbd844099..df577da5c7 100644 --- a/ARM/gcc_clang/def/R7FA4M3AE3CFP.json +++ b/ARM/gcc_clang/def/R7FA4M3AE3CFP.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AF2CBM.json b/ARM/gcc_clang/def/R7FA4M3AF2CBM.json index 3170f7147b..6daddfd1ae 100644 --- a/ARM/gcc_clang/def/R7FA4M3AF2CBM.json +++ b/ARM/gcc_clang/def/R7FA4M3AF2CBM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AF2CBQ.json b/ARM/gcc_clang/def/R7FA4M3AF2CBQ.json index aa0d3e4188..44ed7a9692 100644 --- a/ARM/gcc_clang/def/R7FA4M3AF2CBQ.json +++ b/ARM/gcc_clang/def/R7FA4M3AF2CBQ.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AF3CBM.json b/ARM/gcc_clang/def/R7FA4M3AF3CBM.json index 1ab6f303ac..b376c13cde 100644 --- a/ARM/gcc_clang/def/R7FA4M3AF3CBM.json +++ b/ARM/gcc_clang/def/R7FA4M3AF3CBM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AF3CBQ.json b/ARM/gcc_clang/def/R7FA4M3AF3CBQ.json index e290d0a59b..c6c72e6809 100644 --- a/ARM/gcc_clang/def/R7FA4M3AF3CBQ.json +++ b/ARM/gcc_clang/def/R7FA4M3AF3CBQ.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AF3CFB.json b/ARM/gcc_clang/def/R7FA4M3AF3CFB.json index fa13be999a..c1108700a2 100644 --- a/ARM/gcc_clang/def/R7FA4M3AF3CFB.json +++ b/ARM/gcc_clang/def/R7FA4M3AF3CFB.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AF3CFM.json b/ARM/gcc_clang/def/R7FA4M3AF3CFM.json index 293520ad57..950a9a0519 100644 --- a/ARM/gcc_clang/def/R7FA4M3AF3CFM.json +++ b/ARM/gcc_clang/def/R7FA4M3AF3CFM.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA4M3AF3CFP.json b/ARM/gcc_clang/def/R7FA4M3AF3CFP.json index d0690f8a46..d622668000 100644 --- a/ARM/gcc_clang/def/R7FA4M3AF3CFP.json +++ b/ARM/gcc_clang/def/R7FA4M3AF3CFP.json @@ -723,6 +723,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AD2CBM.json b/ARM/gcc_clang/def/R7FA6M4AD2CBM.json index 2421839c9f..e6915bc2b7 100644 --- a/ARM/gcc_clang/def/R7FA6M4AD2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M4AD2CBM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AD2CBQ.json b/ARM/gcc_clang/def/R7FA6M4AD2CBQ.json index e856ceb20a..9e0a10e2df 100644 --- a/ARM/gcc_clang/def/R7FA6M4AD2CBQ.json +++ b/ARM/gcc_clang/def/R7FA6M4AD2CBQ.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AD3CBM.json b/ARM/gcc_clang/def/R7FA6M4AD3CBM.json index c90756d4d7..e2b8d2190b 100644 --- a/ARM/gcc_clang/def/R7FA6M4AD3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M4AD3CBM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AD3CBQ.json b/ARM/gcc_clang/def/R7FA6M4AD3CBQ.json index e991d068d9..82d949f2f1 100644 --- a/ARM/gcc_clang/def/R7FA6M4AD3CBQ.json +++ b/ARM/gcc_clang/def/R7FA6M4AD3CBQ.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AD3CFB.json b/ARM/gcc_clang/def/R7FA6M4AD3CFB.json index 9dc83b0d1c..a56a8652db 100644 --- a/ARM/gcc_clang/def/R7FA6M4AD3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M4AD3CFB.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AD3CFM.json b/ARM/gcc_clang/def/R7FA6M4AD3CFM.json index 013c60aa14..8222e668f6 100644 --- a/ARM/gcc_clang/def/R7FA6M4AD3CFM.json +++ b/ARM/gcc_clang/def/R7FA6M4AD3CFM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AD3CFP.json b/ARM/gcc_clang/def/R7FA6M4AD3CFP.json index 95433beb54..83cbbdefb4 100644 --- a/ARM/gcc_clang/def/R7FA6M4AD3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M4AD3CFP.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AE2CBM.json b/ARM/gcc_clang/def/R7FA6M4AE2CBM.json index ab301f2268..de80952643 100644 --- a/ARM/gcc_clang/def/R7FA6M4AE2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M4AE2CBM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AE2CBQ.json b/ARM/gcc_clang/def/R7FA6M4AE2CBQ.json index 4a8995b193..ef37ca92f8 100644 --- a/ARM/gcc_clang/def/R7FA6M4AE2CBQ.json +++ b/ARM/gcc_clang/def/R7FA6M4AE2CBQ.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AE3CBM.json b/ARM/gcc_clang/def/R7FA6M4AE3CBM.json index edb1a06e03..dd647ff24c 100644 --- a/ARM/gcc_clang/def/R7FA6M4AE3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M4AE3CBM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AE3CBQ.json b/ARM/gcc_clang/def/R7FA6M4AE3CBQ.json index a68a251174..cca0258096 100644 --- a/ARM/gcc_clang/def/R7FA6M4AE3CBQ.json +++ b/ARM/gcc_clang/def/R7FA6M4AE3CBQ.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AE3CFB.json b/ARM/gcc_clang/def/R7FA6M4AE3CFB.json index 42b203a126..45cbb0be7c 100644 --- a/ARM/gcc_clang/def/R7FA6M4AE3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M4AE3CFB.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AE3CFM.json b/ARM/gcc_clang/def/R7FA6M4AE3CFM.json index 4f020719de..608bf7e65d 100644 --- a/ARM/gcc_clang/def/R7FA6M4AE3CFM.json +++ b/ARM/gcc_clang/def/R7FA6M4AE3CFM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AE3CFP.json b/ARM/gcc_clang/def/R7FA6M4AE3CFP.json index 424510be7d..45a667a5da 100644 --- a/ARM/gcc_clang/def/R7FA6M4AE3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M4AE3CFP.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AF2CBM.json b/ARM/gcc_clang/def/R7FA6M4AF2CBM.json index 5757f681b7..4587dad456 100644 --- a/ARM/gcc_clang/def/R7FA6M4AF2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M4AF2CBM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AF2CBQ.json b/ARM/gcc_clang/def/R7FA6M4AF2CBQ.json index 2a77fb02b7..e5b35dd37a 100644 --- a/ARM/gcc_clang/def/R7FA6M4AF2CBQ.json +++ b/ARM/gcc_clang/def/R7FA6M4AF2CBQ.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AF3CBM.json b/ARM/gcc_clang/def/R7FA6M4AF3CBM.json index 3e16db4870..16785e22cb 100644 --- a/ARM/gcc_clang/def/R7FA6M4AF3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M4AF3CBM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AF3CBQ.json b/ARM/gcc_clang/def/R7FA6M4AF3CBQ.json index 5ad495d58e..eaac36e475 100644 --- a/ARM/gcc_clang/def/R7FA6M4AF3CBQ.json +++ b/ARM/gcc_clang/def/R7FA6M4AF3CBQ.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AF3CFB.json b/ARM/gcc_clang/def/R7FA6M4AF3CFB.json index ea066f2b6b..32809b4e10 100644 --- a/ARM/gcc_clang/def/R7FA6M4AF3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M4AF3CFB.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AF3CFM.json b/ARM/gcc_clang/def/R7FA6M4AF3CFM.json index 2d64110c9f..4746f6c3b6 100644 --- a/ARM/gcc_clang/def/R7FA6M4AF3CFM.json +++ b/ARM/gcc_clang/def/R7FA6M4AF3CFM.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M4AF3CFP.json b/ARM/gcc_clang/def/R7FA6M4AF3CFP.json index 50e2ed7ee0..2af8706b77 100644 --- a/ARM/gcc_clang/def/R7FA6M4AF3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M4AF3CFP.json @@ -760,6 +760,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AG2CBG.json b/ARM/gcc_clang/def/R7FA6M5AG2CBG.json index 3cf9169cd2..aa5c2cb060 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5AG2CBG.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AG2CBM.json b/ARM/gcc_clang/def/R7FA6M5AG2CBM.json index 0e6cee5ffc..11988a51f8 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AG2CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CBM.json b/ARM/gcc_clang/def/R7FA6M5AG3CBM.json index f13dfb7bbb..2464fd6c8a 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFB.json b/ARM/gcc_clang/def/R7FA6M5AG3CFB.json index c6da1a91bf..4ae60fcf42 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFB.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFC.json b/ARM/gcc_clang/def/R7FA6M5AG3CFC.json index 6db5239255..cd31461263 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFC.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFP.json b/ARM/gcc_clang/def/R7FA6M5AG3CFP.json index 821b664983..3c572e8a14 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFP.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AH2CBG.json b/ARM/gcc_clang/def/R7FA6M5AH2CBG.json index b24a6a31b2..761625e5ef 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5AH2CBG.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AH2CBM.json b/ARM/gcc_clang/def/R7FA6M5AH2CBM.json index e37a1f532f..44620c1f9f 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AH2CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CBM.json b/ARM/gcc_clang/def/R7FA6M5AH3CBM.json index 7294c54ed5..959a20c131 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFB.json b/ARM/gcc_clang/def/R7FA6M5AH3CFB.json index 50423cff20..096df8f1f9 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFB.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFC.json b/ARM/gcc_clang/def/R7FA6M5AH3CFC.json index 20d1feffe7..b5ddcada5b 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFC.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFP.json b/ARM/gcc_clang/def/R7FA6M5AH3CFP.json index f13eb0a791..0cb6415a6d 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFP.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BF2CBG.json b/ARM/gcc_clang/def/R7FA6M5BF2CBG.json index 02aa7d2e9e..aea5e7ad0a 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BF2CBG.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BF2CBM.json b/ARM/gcc_clang/def/R7FA6M5BF2CBM.json index fe7ca81f03..81d683ec48 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BF2CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CBM.json b/ARM/gcc_clang/def/R7FA6M5BF3CBM.json index 7aa8654c06..c04067ac5e 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFB.json b/ARM/gcc_clang/def/R7FA6M5BF3CFB.json index 3be1890036..18b48e0f1f 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFB.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFC.json b/ARM/gcc_clang/def/R7FA6M5BF3CFC.json index ea311cdd89..a082acd712 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFC.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFP.json b/ARM/gcc_clang/def/R7FA6M5BF3CFP.json index 5c4735a9b6..cf9ec72c74 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFP.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BG2CBG.json b/ARM/gcc_clang/def/R7FA6M5BG2CBG.json index b8ac81473d..f040e0e352 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BG2CBG.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BG2CBM.json b/ARM/gcc_clang/def/R7FA6M5BG2CBM.json index 05fb19e624..b93481f77f 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BG2CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CBM.json b/ARM/gcc_clang/def/R7FA6M5BG3CBM.json index 93ede18c80..7516f99050 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFB.json b/ARM/gcc_clang/def/R7FA6M5BG3CFB.json index f38f10ec3e..d6d0d0084f 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFB.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFC.json b/ARM/gcc_clang/def/R7FA6M5BG3CFC.json index 9fe357a437..36f79a8b51 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFC.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFP.json b/ARM/gcc_clang/def/R7FA6M5BG3CFP.json index 2616c03343..723445efde 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFP.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BH2CBG.json b/ARM/gcc_clang/def/R7FA6M5BH2CBG.json index 6d8ee20f13..dd058ba050 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BH2CBG.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BH2CBM.json b/ARM/gcc_clang/def/R7FA6M5BH2CBM.json index 6f1eae0759..e31a7591e7 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BH2CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CBM.json b/ARM/gcc_clang/def/R7FA6M5BH3CBM.json index d0b098056e..4edcc4e0e5 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CBM.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFB.json b/ARM/gcc_clang/def/R7FA6M5BH3CFB.json index cc0692eb9f..c396357bda 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFB.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFC.json b/ARM/gcc_clang/def/R7FA6M5BH3CFC.json index d2df6a7125..9b5d8511c8 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFC.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFP.json b/ARM/gcc_clang/def/R7FA6M5BH3CFP.json index 05dd97b5a2..debb26211f 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFP.json @@ -609,7 +609,7 @@ "label": "High-speed on-chip oscillator control register" }, { - "address": "4001e000", + "address": "4001e037", "default": "00000000", "fields": [ { @@ -810,6 +810,252 @@ "unused": "00000008", "label": "Clock out control register" }, + { + "address": "4001e048", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PL2IDIV", + "label": "PLL2 Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "\u2215 1 (value after reset)", + "value": "0" + }, + { + "label": "\u2215 2", + "value": "1" + }, + { + "label": "\u2215 3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PL2SRCSEL", + "label": "PLL2 Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLL2MUL", + "label": "PLL2 Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLL2CCR", + "unused": "0000c0ec", + "label": "PLL2 Clock Control Register" + }, + { + "address": "4001e04a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLL2STP", + "label": "PLL2 Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL2 is operating", + "value": "0" + }, + { + "label": "PLL2 is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLL2CR", + "unused": "000000fe", + "label": "PLL2 Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AB3CFL.json b/ARM/gcc_clang/def/R7FA6T2AB3CFL.json index 32e30cb618..7c186f0a90 100644 --- a/ARM/gcc_clang/def/R7FA6T2AB3CFL.json +++ b/ARM/gcc_clang/def/R7FA6T2AB3CFL.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AB3CFM.json b/ARM/gcc_clang/def/R7FA6T2AB3CFM.json index 330e7bac52..c3d065b89b 100644 --- a/ARM/gcc_clang/def/R7FA6T2AB3CFM.json +++ b/ARM/gcc_clang/def/R7FA6T2AB3CFM.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AB3CFP.json b/ARM/gcc_clang/def/R7FA6T2AB3CFP.json index 7c9adfe601..55f80552ed 100644 --- a/ARM/gcc_clang/def/R7FA6T2AB3CFP.json +++ b/ARM/gcc_clang/def/R7FA6T2AB3CFP.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AB3CNB.json b/ARM/gcc_clang/def/R7FA6T2AB3CNB.json index 9f2291316d..12d7defcbb 100644 --- a/ARM/gcc_clang/def/R7FA6T2AB3CNB.json +++ b/ARM/gcc_clang/def/R7FA6T2AB3CNB.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AB3CNE.json b/ARM/gcc_clang/def/R7FA6T2AB3CNE.json index c90e8e5ad5..1f3ddc505d 100644 --- a/ARM/gcc_clang/def/R7FA6T2AB3CNE.json +++ b/ARM/gcc_clang/def/R7FA6T2AB3CNE.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AD3CFL.json b/ARM/gcc_clang/def/R7FA6T2AD3CFL.json index caf22d2aa2..52f04923bb 100644 --- a/ARM/gcc_clang/def/R7FA6T2AD3CFL.json +++ b/ARM/gcc_clang/def/R7FA6T2AD3CFL.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AD3CFM.json b/ARM/gcc_clang/def/R7FA6T2AD3CFM.json index 6a279f5073..9f10e48694 100644 --- a/ARM/gcc_clang/def/R7FA6T2AD3CFM.json +++ b/ARM/gcc_clang/def/R7FA6T2AD3CFM.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AD3CFP.json b/ARM/gcc_clang/def/R7FA6T2AD3CFP.json index 4fd62ed2bf..bd1118fa7f 100644 --- a/ARM/gcc_clang/def/R7FA6T2AD3CFP.json +++ b/ARM/gcc_clang/def/R7FA6T2AD3CFP.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AD3CNB.json b/ARM/gcc_clang/def/R7FA6T2AD3CNB.json index 1cdb3ee231..81b48d1ddc 100644 --- a/ARM/gcc_clang/def/R7FA6T2AD3CNB.json +++ b/ARM/gcc_clang/def/R7FA6T2AD3CNB.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2AD3CNE.json b/ARM/gcc_clang/def/R7FA6T2AD3CNE.json index 94fbed7d3c..c916170051 100644 --- a/ARM/gcc_clang/def/R7FA6T2AD3CNE.json +++ b/ARM/gcc_clang/def/R7FA6T2AD3CNE.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BB3CFL.json b/ARM/gcc_clang/def/R7FA6T2BB3CFL.json index 65d438b28b..7de3ec5be7 100644 --- a/ARM/gcc_clang/def/R7FA6T2BB3CFL.json +++ b/ARM/gcc_clang/def/R7FA6T2BB3CFL.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BB3CFM.json b/ARM/gcc_clang/def/R7FA6T2BB3CFM.json index f20101ffec..4e55809a75 100644 --- a/ARM/gcc_clang/def/R7FA6T2BB3CFM.json +++ b/ARM/gcc_clang/def/R7FA6T2BB3CFM.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BB3CFP.json b/ARM/gcc_clang/def/R7FA6T2BB3CFP.json index 9f99be7f0e..2d21e527c0 100644 --- a/ARM/gcc_clang/def/R7FA6T2BB3CFP.json +++ b/ARM/gcc_clang/def/R7FA6T2BB3CFP.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BB3CNB.json b/ARM/gcc_clang/def/R7FA6T2BB3CNB.json index 87e4e14779..2c555ef942 100644 --- a/ARM/gcc_clang/def/R7FA6T2BB3CNB.json +++ b/ARM/gcc_clang/def/R7FA6T2BB3CNB.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BB3CNE.json b/ARM/gcc_clang/def/R7FA6T2BB3CNE.json index 1fa1e2e51c..c9eb999057 100644 --- a/ARM/gcc_clang/def/R7FA6T2BB3CNE.json +++ b/ARM/gcc_clang/def/R7FA6T2BB3CNE.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BD3CFL.json b/ARM/gcc_clang/def/R7FA6T2BD3CFL.json index a5e2bc1a99..9fecda2e67 100644 --- a/ARM/gcc_clang/def/R7FA6T2BD3CFL.json +++ b/ARM/gcc_clang/def/R7FA6T2BD3CFL.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BD3CFM.json b/ARM/gcc_clang/def/R7FA6T2BD3CFM.json index 4c8c1bea25..cf9c39b7d4 100644 --- a/ARM/gcc_clang/def/R7FA6T2BD3CFM.json +++ b/ARM/gcc_clang/def/R7FA6T2BD3CFM.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BD3CFP.json b/ARM/gcc_clang/def/R7FA6T2BD3CFP.json index 9f22d8f049..1cf46f9afe 100644 --- a/ARM/gcc_clang/def/R7FA6T2BD3CFP.json +++ b/ARM/gcc_clang/def/R7FA6T2BD3CFP.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BD3CNB.json b/ARM/gcc_clang/def/R7FA6T2BD3CNB.json index f6e2813e2c..5ee911b814 100644 --- a/ARM/gcc_clang/def/R7FA6T2BD3CNB.json +++ b/ARM/gcc_clang/def/R7FA6T2BD3CNB.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7FA6T2BD3CNE.json b/ARM/gcc_clang/def/R7FA6T2BD3CNE.json index 4b54c29a5c..9ad644ea4e 100644 --- a/ARM/gcc_clang/def/R7FA6T2BD3CNE.json +++ b/ARM/gcc_clang/def/R7FA6T2BD3CNE.json @@ -495,7 +495,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -961,6 +961,86 @@ "unused": "000000fe", "label": "Pll2 control register" }, + { + "address": "4001e070", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "IICCKDIV", + "label": "IIC clock (IICCLK) Division Select", + "mask": "7", + "settings": [ + { + "label": "/1 (value after reset)", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/4", + "value": "2" + }, + { + "label": "/6", + "value": "3" + }, + { + "label": "/8", + "value": "4" + } + ] + } + ], + "key": "SYSTEM_IICCKDIVCR", + "unused": "000000f8", + "label": "IIC Clock Division Control Register" + }, + { + "address": "4001e078", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "IICCKSEL", + "label": "IIC clock (IICCLK) Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "PLL", + "value": "5" + }, + { + "label": "PLL2", + "value": "6" + } + ] + } + ], + "key": "SYSTEM_IICCKCR", + "unused": "00000038", + "label": "IIC Clock Control Register" + }, { "address": "4001e0a0", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8D2JRDSAJ.json b/ARM/gcc_clang/def/R7JA8D2JRDSAJ.json index b43ab5bf45..929d21bc41 100644 --- a/ARM/gcc_clang/def/R7JA8D2JRDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8D2JRDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8D2JRLSAJ.json b/ARM/gcc_clang/def/R7JA8D2JRLSAJ.json index e632c9d0b9..51951c899e 100644 --- a/ARM/gcc_clang/def/R7JA8D2JRLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8D2JRLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8D2JSDSAJ.json b/ARM/gcc_clang/def/R7JA8D2JSDSAJ.json index b1f1354689..42618042b4 100644 --- a/ARM/gcc_clang/def/R7JA8D2JSDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8D2JSDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8D2JSLSAJ.json b/ARM/gcc_clang/def/R7JA8D2JSLSAJ.json index 56e7556df4..7d11dbb566 100644 --- a/ARM/gcc_clang/def/R7JA8D2JSLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8D2JSLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8D2KRDSAJ.json b/ARM/gcc_clang/def/R7JA8D2KRDSAJ.json index a3fbea6518..90d1a357e7 100644 --- a/ARM/gcc_clang/def/R7JA8D2KRDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8D2KRDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8D2KRLSAJ.json b/ARM/gcc_clang/def/R7JA8D2KRLSAJ.json index df9409b8da..3247e769e6 100644 --- a/ARM/gcc_clang/def/R7JA8D2KRLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8D2KRLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8D2KSDSAJ.json b/ARM/gcc_clang/def/R7JA8D2KSDSAJ.json index b389ad394b..73832a1d41 100644 --- a/ARM/gcc_clang/def/R7JA8D2KSDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8D2KSDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8D2KSLSAJ.json b/ARM/gcc_clang/def/R7JA8D2KSLSAJ.json index 2958792485..52011c2afe 100644 --- a/ARM/gcc_clang/def/R7JA8D2KSLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8D2KSLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8M2JRDSAJ.json b/ARM/gcc_clang/def/R7JA8M2JRDSAJ.json index 527e79df29..f8cf3b33b9 100644 --- a/ARM/gcc_clang/def/R7JA8M2JRDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8M2JRDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8M2JRLSAJ.json b/ARM/gcc_clang/def/R7JA8M2JRLSAJ.json index 5a75a5b99f..35418d4528 100644 --- a/ARM/gcc_clang/def/R7JA8M2JRLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8M2JRLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8M2JSDSAJ.json b/ARM/gcc_clang/def/R7JA8M2JSDSAJ.json index 16fdac6a05..47cf4ccf81 100644 --- a/ARM/gcc_clang/def/R7JA8M2JSDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8M2JSDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8M2JSLSAJ.json b/ARM/gcc_clang/def/R7JA8M2JSLSAJ.json index 562d1ecf44..7d8724efa0 100644 --- a/ARM/gcc_clang/def/R7JA8M2JSLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8M2JSLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8P1JRDSAJ.json b/ARM/gcc_clang/def/R7JA8P1JRDSAJ.json index 967aab073a..438833f7e2 100644 --- a/ARM/gcc_clang/def/R7JA8P1JRDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8P1JRDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8P1JRLSAJ.json b/ARM/gcc_clang/def/R7JA8P1JRLSAJ.json index 5def685f54..4fa5bd2fde 100644 --- a/ARM/gcc_clang/def/R7JA8P1JRLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8P1JRLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8P1JSDSAJ.json b/ARM/gcc_clang/def/R7JA8P1JSDSAJ.json index d62dd8b26e..dc68db56ff 100644 --- a/ARM/gcc_clang/def/R7JA8P1JSDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8P1JSDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8P1JSLSAJ.json b/ARM/gcc_clang/def/R7JA8P1JSLSAJ.json index 50b3992403..825126b5da 100644 --- a/ARM/gcc_clang/def/R7JA8P1JSLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8P1JSLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8P1KRDSAJ.json b/ARM/gcc_clang/def/R7JA8P1KRDSAJ.json index a55b841014..94139d46f9 100644 --- a/ARM/gcc_clang/def/R7JA8P1KRDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8P1KRDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8P1KRLSAJ.json b/ARM/gcc_clang/def/R7JA8P1KRLSAJ.json index 72e002654c..57f194cc44 100644 --- a/ARM/gcc_clang/def/R7JA8P1KRLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8P1KRLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8P1KSDSAJ.json b/ARM/gcc_clang/def/R7JA8P1KSDSAJ.json index 915bfe267f..4585b309d0 100644 --- a/ARM/gcc_clang/def/R7JA8P1KSDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8P1KSDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8P1KSLSAJ.json b/ARM/gcc_clang/def/R7JA8P1KSLSAJ.json index 18eaf7bf7a..cfc765f38a 100644 --- a/ARM/gcc_clang/def/R7JA8P1KSLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8P1KSLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8T2JRDSAJ.json b/ARM/gcc_clang/def/R7JA8T2JRDSAJ.json index f337770a7f..ea8a5c1d8d 100644 --- a/ARM/gcc_clang/def/R7JA8T2JRDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8T2JRDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8T2JRLSAJ.json b/ARM/gcc_clang/def/R7JA8T2JRLSAJ.json index e647f06542..46492f40da 100644 --- a/ARM/gcc_clang/def/R7JA8T2JRLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8T2JRLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8T2JSDSAJ.json b/ARM/gcc_clang/def/R7JA8T2JSDSAJ.json index b4d69aa67f..abe90ed4ca 100644 --- a/ARM/gcc_clang/def/R7JA8T2JSDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8T2JSDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8T2JSLSAJ.json b/ARM/gcc_clang/def/R7JA8T2JSLSAJ.json index ecbd49431e..c21f62ce3c 100644 --- a/ARM/gcc_clang/def/R7JA8T2JSLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8T2JSLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8T2LRDSAJ.json b/ARM/gcc_clang/def/R7JA8T2LRDSAJ.json index cd4820cfc8..53a0f3c1d5 100644 --- a/ARM/gcc_clang/def/R7JA8T2LRDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8T2LRDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8T2LRLSAJ.json b/ARM/gcc_clang/def/R7JA8T2LRLSAJ.json index 7b40e512b9..03fd556e21 100644 --- a/ARM/gcc_clang/def/R7JA8T2LRLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8T2LRLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8T2LSDSAJ.json b/ARM/gcc_clang/def/R7JA8T2LSDSAJ.json index 4567f6cc91..f437a6c166 100644 --- a/ARM/gcc_clang/def/R7JA8T2LSDSAJ.json +++ b/ARM/gcc_clang/def/R7JA8T2LSDSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7JA8T2LSLSAJ.json b/ARM/gcc_clang/def/R7JA8T2LSLSAJ.json index c401dab111..4c19183352 100644 --- a/ARM/gcc_clang/def/R7JA8T2LSLSAJ.json +++ b/ARM/gcc_clang/def/R7JA8T2LSLSAJ.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2ADDCAB.json b/ARM/gcc_clang/def/R7KA8D2ADDCAB.json index 31450ea575..154a5c9259 100644 --- a/ARM/gcc_clang/def/R7KA8D2ADDCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2ADDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2ADDCAC.json b/ARM/gcc_clang/def/R7KA8D2ADDCAC.json index 9b6d7eb91b..fd2602c3c2 100644 --- a/ARM/gcc_clang/def/R7KA8D2ADDCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2ADDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2ADLCAB.json b/ARM/gcc_clang/def/R7KA8D2ADLCAB.json index bc299d3dc1..c68a11037c 100644 --- a/ARM/gcc_clang/def/R7KA8D2ADLCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2ADLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2ADLCAC.json b/ARM/gcc_clang/def/R7KA8D2ADLCAC.json index 80eae0d32d..210a79c917 100644 --- a/ARM/gcc_clang/def/R7KA8D2ADLCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2ADLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2AFDCAB.json b/ARM/gcc_clang/def/R7KA8D2AFDCAB.json index 2aece6eb44..dccec7ff0a 100644 --- a/ARM/gcc_clang/def/R7KA8D2AFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2AFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2AFDCAC.json b/ARM/gcc_clang/def/R7KA8D2AFDCAC.json index 10238dcdf9..677aef94b4 100644 --- a/ARM/gcc_clang/def/R7KA8D2AFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2AFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2AFLCAB.json b/ARM/gcc_clang/def/R7KA8D2AFLCAB.json index ad6230423a..d3c3a9721c 100644 --- a/ARM/gcc_clang/def/R7KA8D2AFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2AFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2AFLCAC.json b/ARM/gcc_clang/def/R7KA8D2AFLCAC.json index a902c3b364..65fbb54121 100644 --- a/ARM/gcc_clang/def/R7KA8D2AFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2AFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2BDDCAB.json b/ARM/gcc_clang/def/R7KA8D2BDDCAB.json index 62de7429c0..0fb62fc498 100644 --- a/ARM/gcc_clang/def/R7KA8D2BDDCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2BDDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2BDDCAC.json b/ARM/gcc_clang/def/R7KA8D2BDDCAC.json index 05ec77bd36..4c9fc0d3fc 100644 --- a/ARM/gcc_clang/def/R7KA8D2BDDCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2BDDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2BDLCAB.json b/ARM/gcc_clang/def/R7KA8D2BDLCAB.json index 19ec5e2b28..51aebcdf77 100644 --- a/ARM/gcc_clang/def/R7KA8D2BDLCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2BDLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2BDLCAC.json b/ARM/gcc_clang/def/R7KA8D2BDLCAC.json index fbd5dcd9d9..4e88183a4c 100644 --- a/ARM/gcc_clang/def/R7KA8D2BDLCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2BDLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2BFDCAB.json b/ARM/gcc_clang/def/R7KA8D2BFDCAB.json index daa527835e..b087888a62 100644 --- a/ARM/gcc_clang/def/R7KA8D2BFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2BFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2BFDCAC.json b/ARM/gcc_clang/def/R7KA8D2BFDCAC.json index 415ee92d6a..e3fea0c195 100644 --- a/ARM/gcc_clang/def/R7KA8D2BFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2BFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2BFLCAB.json b/ARM/gcc_clang/def/R7KA8D2BFLCAB.json index 997637d9d0..2eeaf3c66d 100644 --- a/ARM/gcc_clang/def/R7KA8D2BFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2BFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2BFLCAC.json b/ARM/gcc_clang/def/R7KA8D2BFLCAC.json index 6e146f4abc..2babeba315 100644 --- a/ARM/gcc_clang/def/R7KA8D2BFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2BFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2JFDCAB.json b/ARM/gcc_clang/def/R7KA8D2JFDCAB.json index 7d5a071e80..2cb3cfbbd6 100644 --- a/ARM/gcc_clang/def/R7KA8D2JFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2JFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2JFDCAC.json b/ARM/gcc_clang/def/R7KA8D2JFDCAC.json index f62df0e4b3..69d12f58f3 100644 --- a/ARM/gcc_clang/def/R7KA8D2JFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2JFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2JFLCAB.json b/ARM/gcc_clang/def/R7KA8D2JFLCAB.json index e9ad7f6868..cf8e4112f3 100644 --- a/ARM/gcc_clang/def/R7KA8D2JFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2JFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2JFLCAC.json b/ARM/gcc_clang/def/R7KA8D2JFLCAC.json index fcf2e6383b..7b1e3cfcba 100644 --- a/ARM/gcc_clang/def/R7KA8D2JFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2JFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2KFDCAB.json b/ARM/gcc_clang/def/R7KA8D2KFDCAB.json index b7faba4c4a..401dcd9bc3 100644 --- a/ARM/gcc_clang/def/R7KA8D2KFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2KFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2KFDCAC.json b/ARM/gcc_clang/def/R7KA8D2KFDCAC.json index fe6b712025..e796613bca 100644 --- a/ARM/gcc_clang/def/R7KA8D2KFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2KFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2KFLCAB.json b/ARM/gcc_clang/def/R7KA8D2KFLCAB.json index efc122ec1b..6912cfbc3b 100644 --- a/ARM/gcc_clang/def/R7KA8D2KFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8D2KFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8D2KFLCAC.json b/ARM/gcc_clang/def/R7KA8D2KFLCAC.json index b0c4a3278f..3d34522866 100644 --- a/ARM/gcc_clang/def/R7KA8D2KFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8D2KFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2ADDCAB.json b/ARM/gcc_clang/def/R7KA8M2ADDCAB.json index 17846e7aa2..9068528ca7 100644 --- a/ARM/gcc_clang/def/R7KA8M2ADDCAB.json +++ b/ARM/gcc_clang/def/R7KA8M2ADDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2ADDCAC.json b/ARM/gcc_clang/def/R7KA8M2ADDCAC.json index 6b2b91ca33..cccab82f97 100644 --- a/ARM/gcc_clang/def/R7KA8M2ADDCAC.json +++ b/ARM/gcc_clang/def/R7KA8M2ADDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2ADECAB.json b/ARM/gcc_clang/def/R7KA8M2ADECAB.json index a0731b0b66..52020122ad 100644 --- a/ARM/gcc_clang/def/R7KA8M2ADECAB.json +++ b/ARM/gcc_clang/def/R7KA8M2ADECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2ADECAC.json b/ARM/gcc_clang/def/R7KA8M2ADECAC.json index 488c97d52f..886e29b5c8 100644 --- a/ARM/gcc_clang/def/R7KA8M2ADECAC.json +++ b/ARM/gcc_clang/def/R7KA8M2ADECAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2ADECHC.json b/ARM/gcc_clang/def/R7KA8M2ADECHC.json index 0341e97a2e..e8a92bada3 100644 --- a/ARM/gcc_clang/def/R7KA8M2ADECHC.json +++ b/ARM/gcc_clang/def/R7KA8M2ADECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2ADLCAB.json b/ARM/gcc_clang/def/R7KA8M2ADLCAB.json index 5b51f2d9c6..75de8a523b 100644 --- a/ARM/gcc_clang/def/R7KA8M2ADLCAB.json +++ b/ARM/gcc_clang/def/R7KA8M2ADLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2ADLCAC.json b/ARM/gcc_clang/def/R7KA8M2ADLCAC.json index 0540be29eb..702a4bf609 100644 --- a/ARM/gcc_clang/def/R7KA8M2ADLCAC.json +++ b/ARM/gcc_clang/def/R7KA8M2ADLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2AFDCAB.json b/ARM/gcc_clang/def/R7KA8M2AFDCAB.json index d149036796..9b95ef00dc 100644 --- a/ARM/gcc_clang/def/R7KA8M2AFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8M2AFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2AFDCAC.json b/ARM/gcc_clang/def/R7KA8M2AFDCAC.json index 0ab971f68f..1bb07941d2 100644 --- a/ARM/gcc_clang/def/R7KA8M2AFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8M2AFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2AFECAB.json b/ARM/gcc_clang/def/R7KA8M2AFECAB.json index 281269463e..8937a550b7 100644 --- a/ARM/gcc_clang/def/R7KA8M2AFECAB.json +++ b/ARM/gcc_clang/def/R7KA8M2AFECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2AFECAC.json b/ARM/gcc_clang/def/R7KA8M2AFECAC.json index fba51e4466..f60ec2d141 100644 --- a/ARM/gcc_clang/def/R7KA8M2AFECAC.json +++ b/ARM/gcc_clang/def/R7KA8M2AFECAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2AFECHC.json b/ARM/gcc_clang/def/R7KA8M2AFECHC.json index 8e39877b11..0fd7283342 100644 --- a/ARM/gcc_clang/def/R7KA8M2AFECHC.json +++ b/ARM/gcc_clang/def/R7KA8M2AFECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2AFLCAB.json b/ARM/gcc_clang/def/R7KA8M2AFLCAB.json index 2410581776..218964f8e3 100644 --- a/ARM/gcc_clang/def/R7KA8M2AFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8M2AFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2AFLCAC.json b/ARM/gcc_clang/def/R7KA8M2AFLCAC.json index 168ed2450e..58724584fb 100644 --- a/ARM/gcc_clang/def/R7KA8M2AFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8M2AFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2JFDCAB.json b/ARM/gcc_clang/def/R7KA8M2JFDCAB.json index 3479c5eb36..9574f551be 100644 --- a/ARM/gcc_clang/def/R7KA8M2JFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8M2JFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2JFDCAC.json b/ARM/gcc_clang/def/R7KA8M2JFDCAC.json index 8d66437e51..52dd0597d5 100644 --- a/ARM/gcc_clang/def/R7KA8M2JFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8M2JFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2JFECAB.json b/ARM/gcc_clang/def/R7KA8M2JFECAB.json index 9eb110e1eb..e59c8292a0 100644 --- a/ARM/gcc_clang/def/R7KA8M2JFECAB.json +++ b/ARM/gcc_clang/def/R7KA8M2JFECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2JFECAC.json b/ARM/gcc_clang/def/R7KA8M2JFECAC.json index 47a59a88d6..377215eef6 100644 --- a/ARM/gcc_clang/def/R7KA8M2JFECAC.json +++ b/ARM/gcc_clang/def/R7KA8M2JFECAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2JFECHC.json b/ARM/gcc_clang/def/R7KA8M2JFECHC.json index 513481b43a..00a748cc19 100644 --- a/ARM/gcc_clang/def/R7KA8M2JFECHC.json +++ b/ARM/gcc_clang/def/R7KA8M2JFECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2JFLCAB.json b/ARM/gcc_clang/def/R7KA8M2JFLCAB.json index 869e9380df..6caf0c6c96 100644 --- a/ARM/gcc_clang/def/R7KA8M2JFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8M2JFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8M2JFLCAC.json b/ARM/gcc_clang/def/R7KA8M2JFLCAC.json index 060297b413..ddf784fd16 100644 --- a/ARM/gcc_clang/def/R7KA8M2JFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8M2JFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1ADDCAB.json b/ARM/gcc_clang/def/R7KA8P1ADDCAB.json index b74f3c9cb3..bea7458e23 100644 --- a/ARM/gcc_clang/def/R7KA8P1ADDCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1ADDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1ADDCAC.json b/ARM/gcc_clang/def/R7KA8P1ADDCAC.json index 52df9eed59..b295f362e0 100644 --- a/ARM/gcc_clang/def/R7KA8P1ADDCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1ADDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1ADLCAB.json b/ARM/gcc_clang/def/R7KA8P1ADLCAB.json index 5c6f11a00b..f2dd678232 100644 --- a/ARM/gcc_clang/def/R7KA8P1ADLCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1ADLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1ADLCAC.json b/ARM/gcc_clang/def/R7KA8P1ADLCAC.json index c1946b620c..3b7764e16b 100644 --- a/ARM/gcc_clang/def/R7KA8P1ADLCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1ADLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1AFDCAB.json b/ARM/gcc_clang/def/R7KA8P1AFDCAB.json index 75882be5d4..ad6b6dd5fd 100644 --- a/ARM/gcc_clang/def/R7KA8P1AFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1AFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1AFDCAC.json b/ARM/gcc_clang/def/R7KA8P1AFDCAC.json index 9aec8938dd..5858fef062 100644 --- a/ARM/gcc_clang/def/R7KA8P1AFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1AFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1AFLCAB.json b/ARM/gcc_clang/def/R7KA8P1AFLCAB.json index a557ca0eb7..978b887ede 100644 --- a/ARM/gcc_clang/def/R7KA8P1AFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1AFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1AFLCAC.json b/ARM/gcc_clang/def/R7KA8P1AFLCAC.json index bc03580612..dc6072f5ca 100644 --- a/ARM/gcc_clang/def/R7KA8P1AFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1AFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1BDDCAB.json b/ARM/gcc_clang/def/R7KA8P1BDDCAB.json index 7a10406899..9269d6f8d4 100644 --- a/ARM/gcc_clang/def/R7KA8P1BDDCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1BDDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1BDDCAC.json b/ARM/gcc_clang/def/R7KA8P1BDDCAC.json index 692c3409da..686407ab7b 100644 --- a/ARM/gcc_clang/def/R7KA8P1BDDCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1BDDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1BDLCAB.json b/ARM/gcc_clang/def/R7KA8P1BDLCAB.json index 4c1fbe332b..c8eb6a5f97 100644 --- a/ARM/gcc_clang/def/R7KA8P1BDLCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1BDLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1BDLCAC.json b/ARM/gcc_clang/def/R7KA8P1BDLCAC.json index 5ace76ec7b..c9bf18d2a5 100644 --- a/ARM/gcc_clang/def/R7KA8P1BDLCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1BDLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1BFDCAB.json b/ARM/gcc_clang/def/R7KA8P1BFDCAB.json index 2a77b71882..0e3edfc990 100644 --- a/ARM/gcc_clang/def/R7KA8P1BFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1BFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1BFDCAC.json b/ARM/gcc_clang/def/R7KA8P1BFDCAC.json index e040f1fa68..2c9160d09b 100644 --- a/ARM/gcc_clang/def/R7KA8P1BFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1BFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1BFLCAB.json b/ARM/gcc_clang/def/R7KA8P1BFLCAB.json index d74b5ce458..b9bccf5a21 100644 --- a/ARM/gcc_clang/def/R7KA8P1BFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1BFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1BFLCAC.json b/ARM/gcc_clang/def/R7KA8P1BFLCAC.json index ca947d08cf..072e376f24 100644 --- a/ARM/gcc_clang/def/R7KA8P1BFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1BFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1JFDCAB.json b/ARM/gcc_clang/def/R7KA8P1JFDCAB.json index bbde05e503..82474f764a 100644 --- a/ARM/gcc_clang/def/R7KA8P1JFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1JFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1JFDCAC.json b/ARM/gcc_clang/def/R7KA8P1JFDCAC.json index 313a4d8710..31adcc6794 100644 --- a/ARM/gcc_clang/def/R7KA8P1JFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1JFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1JFLCAB.json b/ARM/gcc_clang/def/R7KA8P1JFLCAB.json index e8ad29af3b..d5f08a97d6 100644 --- a/ARM/gcc_clang/def/R7KA8P1JFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1JFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1JFLCAC.json b/ARM/gcc_clang/def/R7KA8P1JFLCAC.json index b5cf38ece4..72bfb80323 100644 --- a/ARM/gcc_clang/def/R7KA8P1JFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1JFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1KFDCAB.json b/ARM/gcc_clang/def/R7KA8P1KFDCAB.json index 30d1dadeef..7067b5f6b3 100644 --- a/ARM/gcc_clang/def/R7KA8P1KFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1KFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1KFDCAC.json b/ARM/gcc_clang/def/R7KA8P1KFDCAC.json index b3f0b31e00..fd228fc335 100644 --- a/ARM/gcc_clang/def/R7KA8P1KFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1KFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1KFLCAB.json b/ARM/gcc_clang/def/R7KA8P1KFLCAB.json index c7f83f8c24..391325d765 100644 --- a/ARM/gcc_clang/def/R7KA8P1KFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8P1KFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8P1KFLCAC.json b/ARM/gcc_clang/def/R7KA8P1KFLCAC.json index 7143a60797..9c1dae8379 100644 --- a/ARM/gcc_clang/def/R7KA8P1KFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8P1KFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2ADDCAB.json b/ARM/gcc_clang/def/R7KA8T2ADDCAB.json index f67778ec9d..7a55a78ec5 100644 --- a/ARM/gcc_clang/def/R7KA8T2ADDCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2ADDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2ADECAB.json b/ARM/gcc_clang/def/R7KA8T2ADECAB.json index 6da6c879ae..f1e4adc491 100644 --- a/ARM/gcc_clang/def/R7KA8T2ADECAB.json +++ b/ARM/gcc_clang/def/R7KA8T2ADECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2ADECHC.json b/ARM/gcc_clang/def/R7KA8T2ADECHC.json index 23e11757cd..6b38f19a33 100644 --- a/ARM/gcc_clang/def/R7KA8T2ADECHC.json +++ b/ARM/gcc_clang/def/R7KA8T2ADECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2AFDCAB.json b/ARM/gcc_clang/def/R7KA8T2AFDCAB.json index 47fb035cf2..c504350de6 100644 --- a/ARM/gcc_clang/def/R7KA8T2AFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2AFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2AFDCAC.json b/ARM/gcc_clang/def/R7KA8T2AFDCAC.json index 717d81412f..d572dbc99a 100644 --- a/ARM/gcc_clang/def/R7KA8T2AFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8T2AFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2AFECAB.json b/ARM/gcc_clang/def/R7KA8T2AFECAB.json index 90007ed84b..2bfc24ebd1 100644 --- a/ARM/gcc_clang/def/R7KA8T2AFECAB.json +++ b/ARM/gcc_clang/def/R7KA8T2AFECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2AFECAC.json b/ARM/gcc_clang/def/R7KA8T2AFECAC.json index bc701e5e21..b6ae71cf78 100644 --- a/ARM/gcc_clang/def/R7KA8T2AFECAC.json +++ b/ARM/gcc_clang/def/R7KA8T2AFECAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2AFECHC.json b/ARM/gcc_clang/def/R7KA8T2AFECHC.json index 8cd2e8f06c..e88c1c50ea 100644 --- a/ARM/gcc_clang/def/R7KA8T2AFECHC.json +++ b/ARM/gcc_clang/def/R7KA8T2AFECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2AFLCAB.json b/ARM/gcc_clang/def/R7KA8T2AFLCAB.json index 642085b2fa..f785ec1dcd 100644 --- a/ARM/gcc_clang/def/R7KA8T2AFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2AFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2AFLCAC.json b/ARM/gcc_clang/def/R7KA8T2AFLCAC.json index 4547507626..b5b919b959 100644 --- a/ARM/gcc_clang/def/R7KA8T2AFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8T2AFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CDDCAB.json b/ARM/gcc_clang/def/R7KA8T2CDDCAB.json index b3604b8a78..41405e91b2 100644 --- a/ARM/gcc_clang/def/R7KA8T2CDDCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2CDDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CDECAB.json b/ARM/gcc_clang/def/R7KA8T2CDECAB.json index 264f14f193..3c185d09a9 100644 --- a/ARM/gcc_clang/def/R7KA8T2CDECAB.json +++ b/ARM/gcc_clang/def/R7KA8T2CDECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CDECHC.json b/ARM/gcc_clang/def/R7KA8T2CDECHC.json index 15d6b50bb4..866d7e4bdc 100644 --- a/ARM/gcc_clang/def/R7KA8T2CDECHC.json +++ b/ARM/gcc_clang/def/R7KA8T2CDECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CFDCAB.json b/ARM/gcc_clang/def/R7KA8T2CFDCAB.json index 0bdcc7e40b..a64f9bd218 100644 --- a/ARM/gcc_clang/def/R7KA8T2CFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2CFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CFDCAC.json b/ARM/gcc_clang/def/R7KA8T2CFDCAC.json index e8326bef72..36be548963 100644 --- a/ARM/gcc_clang/def/R7KA8T2CFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8T2CFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CFECAB.json b/ARM/gcc_clang/def/R7KA8T2CFECAB.json index 32fdd1263d..0b12c13fe8 100644 --- a/ARM/gcc_clang/def/R7KA8T2CFECAB.json +++ b/ARM/gcc_clang/def/R7KA8T2CFECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CFECAC.json b/ARM/gcc_clang/def/R7KA8T2CFECAC.json index 152874744b..643f529828 100644 --- a/ARM/gcc_clang/def/R7KA8T2CFECAC.json +++ b/ARM/gcc_clang/def/R7KA8T2CFECAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CFECHC.json b/ARM/gcc_clang/def/R7KA8T2CFECHC.json index e3d9eddaa0..5f8d591b0c 100644 --- a/ARM/gcc_clang/def/R7KA8T2CFECHC.json +++ b/ARM/gcc_clang/def/R7KA8T2CFECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CFLCAB.json b/ARM/gcc_clang/def/R7KA8T2CFLCAB.json index ac9b36e0e9..2cfde22e9b 100644 --- a/ARM/gcc_clang/def/R7KA8T2CFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2CFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2CFLCAC.json b/ARM/gcc_clang/def/R7KA8T2CFLCAC.json index e23dcf8d70..83409ecb5b 100644 --- a/ARM/gcc_clang/def/R7KA8T2CFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8T2CFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2JFDCAB.json b/ARM/gcc_clang/def/R7KA8T2JFDCAB.json index eb38efc1f7..f219836f60 100644 --- a/ARM/gcc_clang/def/R7KA8T2JFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2JFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2JFDCAC.json b/ARM/gcc_clang/def/R7KA8T2JFDCAC.json index 2507cb5c84..03cfe44ded 100644 --- a/ARM/gcc_clang/def/R7KA8T2JFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8T2JFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2JFECAB.json b/ARM/gcc_clang/def/R7KA8T2JFECAB.json index 2eaf2d8de5..58b58d32e2 100644 --- a/ARM/gcc_clang/def/R7KA8T2JFECAB.json +++ b/ARM/gcc_clang/def/R7KA8T2JFECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2JFECAC.json b/ARM/gcc_clang/def/R7KA8T2JFECAC.json index 30ebdd54d3..1414c4e063 100644 --- a/ARM/gcc_clang/def/R7KA8T2JFECAC.json +++ b/ARM/gcc_clang/def/R7KA8T2JFECAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2JFECHC.json b/ARM/gcc_clang/def/R7KA8T2JFECHC.json index c299e919cb..a6cab2e431 100644 --- a/ARM/gcc_clang/def/R7KA8T2JFECHC.json +++ b/ARM/gcc_clang/def/R7KA8T2JFECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2JFLCAB.json b/ARM/gcc_clang/def/R7KA8T2JFLCAB.json index 1b2957bf00..33dc0f707d 100644 --- a/ARM/gcc_clang/def/R7KA8T2JFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2JFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2JFLCAC.json b/ARM/gcc_clang/def/R7KA8T2JFLCAC.json index 09c082fbaa..29ef48782d 100644 --- a/ARM/gcc_clang/def/R7KA8T2JFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8T2JFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2LFDCAB.json b/ARM/gcc_clang/def/R7KA8T2LFDCAB.json index ed0dfa54bd..2c7a5886df 100644 --- a/ARM/gcc_clang/def/R7KA8T2LFDCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2LFDCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2LFDCAC.json b/ARM/gcc_clang/def/R7KA8T2LFDCAC.json index d7663d80da..88cf1f7993 100644 --- a/ARM/gcc_clang/def/R7KA8T2LFDCAC.json +++ b/ARM/gcc_clang/def/R7KA8T2LFDCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2LFECAB.json b/ARM/gcc_clang/def/R7KA8T2LFECAB.json index 51d0c8fc84..210838fb9c 100644 --- a/ARM/gcc_clang/def/R7KA8T2LFECAB.json +++ b/ARM/gcc_clang/def/R7KA8T2LFECAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2LFECAC.json b/ARM/gcc_clang/def/R7KA8T2LFECAC.json index 1e1789e483..2c1e0a440a 100644 --- a/ARM/gcc_clang/def/R7KA8T2LFECAC.json +++ b/ARM/gcc_clang/def/R7KA8T2LFECAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2LFECHC.json b/ARM/gcc_clang/def/R7KA8T2LFECHC.json index 5d3069d1a5..bc54e25cbd 100644 --- a/ARM/gcc_clang/def/R7KA8T2LFECHC.json +++ b/ARM/gcc_clang/def/R7KA8T2LFECHC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2LFLCAB.json b/ARM/gcc_clang/def/R7KA8T2LFLCAB.json index 75036afccb..64aebe7cbe 100644 --- a/ARM/gcc_clang/def/R7KA8T2LFLCAB.json +++ b/ARM/gcc_clang/def/R7KA8T2LFLCAB.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/def/R7KA8T2LFLCAC.json b/ARM/gcc_clang/def/R7KA8T2LFLCAC.json index 7b7de20a13..8864db8a0b 100644 --- a/ARM/gcc_clang/def/R7KA8T2LFLCAC.json +++ b/ARM/gcc_clang/def/R7KA8T2LFLCAC.json @@ -269,6 +269,59 @@ } ] }, + { + "hidden": false, + "init": "200000", + "key": "PCKE", + "label": "Peripheral Module Clock E (PCLKE) Select", + "mask": "f00000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100000" + }, + { + "label": "x1/4", + "value": "200000" + }, + { + "label": "x1/8", + "value": "300000" + }, + { + "label": "x1/16", + "value": "400000" + }, + { + "label": "x1/32", + "value": "500000" + }, + { + "label": "x1/64", + "value": "600000" + }, + { + "label": "x1/3", + "value": "800000" + }, + { + "label": "x1/6", + "value": "900000" + }, + { + "label": "x1/12", + "value": "a00000" + }, + { + "label": "x1/24", + "value": "b00000" + } + ] + }, { "hidden": false, "init": "3000000", @@ -1338,6 +1391,118 @@ "unused": "00000030", "label": "Spi clock control register" }, + { + "address": "4001e05a", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKDIV", + "label": "ADC Clock (ADCCLK) Division Select", + "mask": "f", + "settings": [ + { + "label": "1/1 (value after reset)", + "value": "0" + }, + { + "label": "1/2", + "value": "1" + }, + { + "label": "1/4", + "value": "2" + }, + { + "label": "1/6", + "value": "3" + }, + { + "label": "1/8", + "value": "4" + }, + { + "label": "1/10", + "value": "7" + }, + { + "label": "1/16", + "value": "8" + }, + { + "label": "1/32", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_ADCCKDIVCR", + "unused": "000000f0", + "label": "ADC Clock Division Control Register" + }, + { + "address": "4001e05b", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "ADCCKSEL", + "label": "ADC Clock (ADCCLK) Source Select", + "mask": "f", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO (value after reset)", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator", + "value": "3" + }, + { + "label": "Sub-clock oscillator", + "value": "4" + }, + { + "label": "PLL1P", + "value": "5" + }, + { + "label": "PLL2P", + "value": "6" + }, + { + "label": "PLL1Q", + "value": "7" + }, + { + "label": "PLL1R", + "value": "8" + }, + { + "label": "PLL2Q", + "value": "9" + }, + { + "label": "PLL2R", + "value": "a" + } + ] + } + ], + "key": "SYSTEM_ADCCKCR", + "unused": "00000030", + "label": "ADC Clock Control Register" + }, { "address": "4001e070", "default": "0", diff --git a/ARM/gcc_clang/system/src/renesas/r7fa6t3bb3cnh/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7fa6t3bb3cnh/init_clock.c index 9ea0852f15..e6cceb0592 100644 --- a/ARM/gcc_clang/system/src/renesas/r7fa6t3bb3cnh/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7fa6t3bb3cnh/init_clock.c @@ -54,7 +54,7 @@ typedef struct uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; @@ -560,22 +560,22 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get I3C clock frequency. switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { case I3C_SOURCE_HOCO: - SYSTEM_Clocks->I3CCK_Frequency = hoco_frequency; + SYSTEM_Clocks->I3CCLK_Frequency = hoco_frequency; break; case I3C_SOURCE_MOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_8MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_8MHZ; break; case I3C_SOURCE_LOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_XTAL: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_20MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_20MHZ; break; case I3C_SOURCE_SUBCLK: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_PLL: - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); break; default: @@ -583,7 +583,7 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { } // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -755,13 +755,19 @@ static void system_clock_configuration() { R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock write protection register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/r7ja8d2/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ja8d2/init_clock.c index 22a87fad0f..28bd0ecf59 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ja8d2/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ja8d2/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -832,123 +823,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: + case PERIPHERAL_SOURCE_MOSC: // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -993,6 +925,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1027,21 +963,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1349,6 +1285,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1363,8 +1315,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ja8m2/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ja8m2/init_clock.c index e2260ea117..21078af754 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ja8m2/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ja8m2/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = {1, 2, 4, 6, 8, 3, 5}; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -815,123 +806,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8M2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -976,6 +908,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1010,21 +946,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1332,6 +1268,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1346,8 +1298,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ja8p1/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ja8p1/init_clock.c index da82e3c3f0..4e0c16cc73 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ja8p1/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ja8p1/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -833,123 +824,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8P1 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -994,6 +926,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1028,21 +964,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1350,6 +1286,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1364,8 +1316,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ja8t2j/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ja8t2j/init_clock.c index 4b8adedc99..9538a39163 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ja8t2j/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ja8t2j/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -831,123 +822,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8T2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -992,6 +924,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1026,21 +962,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1348,6 +1284,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1362,8 +1314,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ja8t2l/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ja8t2l/init_clock.c index 4b8adedc99..9538a39163 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ja8t2l/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ja8t2l/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -831,123 +822,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8T2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -992,6 +924,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1026,21 +962,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1348,6 +1284,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1362,8 +1314,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8d2j/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8d2j/init_clock.c index 22a87fad0f..28bd0ecf59 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8d2j/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8d2j/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -832,123 +823,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: + case PERIPHERAL_SOURCE_MOSC: // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -993,6 +925,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1027,21 +963,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1349,6 +1285,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1363,8 +1315,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8d2k/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8d2k/init_clock.c index 22a87fad0f..28bd0ecf59 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8d2k/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8d2k/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -832,123 +823,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: + case PERIPHERAL_SOURCE_MOSC: // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -993,6 +925,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1027,21 +963,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1349,6 +1285,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1363,8 +1315,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8m2a_chc/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8m2a_chc/init_clock.c index e2260ea117..21078af754 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8m2a_chc/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8m2a_chc/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = {1, 2, 4, 6, 8, 3, 5}; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -815,123 +806,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8M2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -976,6 +908,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1010,21 +946,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1332,6 +1268,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1346,8 +1298,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8m2j/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8m2j/init_clock.c index e2260ea117..21078af754 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8m2j/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8m2j/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = {1, 2, 4, 6, 8, 3, 5}; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -815,123 +806,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8M2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -976,6 +908,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1010,21 +946,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1332,6 +1268,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1346,8 +1298,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8m2jfechc/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8m2jfechc/init_clock.c index e2260ea117..21078af754 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8m2jfechc/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8m2jfechc/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = {1, 2, 4, 6, 8, 3, 5}; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -815,123 +806,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8M2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -976,6 +908,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1010,21 +946,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1332,6 +1268,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1346,8 +1298,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8p1a/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8p1a/init_clock.c index da82e3c3f0..4e0c16cc73 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8p1a/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8p1a/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -833,123 +824,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8P1 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -994,6 +926,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1028,21 +964,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1350,6 +1286,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1364,8 +1316,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8p1b/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8p1b/init_clock.c index da82e3c3f0..4e0c16cc73 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8p1b/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8p1b/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -833,123 +824,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8P1 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -994,6 +926,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1028,21 +964,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1350,6 +1286,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1364,8 +1316,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8p1j/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8p1j/init_clock.c index da82e3c3f0..4e0c16cc73 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8p1j/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8p1j/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -833,123 +824,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8P1 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -994,6 +926,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1028,21 +964,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1350,6 +1286,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1364,8 +1316,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/r7ka8p1k/init_clock.c b/ARM/gcc_clang/system/src/renesas/r7ka8p1k/init_clock.c index da82e3c3f0..4e0c16cc73 100644 --- a/ARM/gcc_clang/system/src/renesas/r7ka8p1k/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/r7ka8p1k/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -833,123 +824,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8P1 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -994,6 +926,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1028,21 +964,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1350,6 +1286,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1364,8 +1316,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/ra4e2/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra4e2/init_clock.c index 3939e6150b..1832e0c561 100644 --- a/ARM/gcc_clang/system/src/renesas/ra4e2/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra4e2/init_clock.c @@ -54,7 +54,7 @@ typedef struct uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; @@ -546,22 +546,22 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get I3C clock frequency. switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { case I3C_SOURCE_HOCO: - SYSTEM_Clocks->I3CCK_Frequency = hoco_frequency; + SYSTEM_Clocks->I3CCLK_Frequency = hoco_frequency; break; case I3C_SOURCE_MOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_8MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_8MHZ; break; case I3C_SOURCE_LOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_XTAL: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_20MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_20MHZ; break; case I3C_SOURCE_SUBCLK: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_PLL: - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); break; default: @@ -569,7 +569,7 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { } // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -741,13 +741,19 @@ static void system_clock_configuration() { R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock write protection register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra4l1/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra4l1/init_clock.c index 4032a40f64..3fe6cbffab 100644 --- a/ARM/gcc_clang/system/src/renesas/ra4l1/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra4l1/init_clock.c @@ -54,7 +54,7 @@ typedef struct uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz uint32_t UARTA0_Frequency; // FSEL0 clock frequency in Hz uint32_t UARTA1_Frequency; // FSEL1 clock frequency in Hz } SYSTEM_ClocksTypeDef; @@ -628,22 +628,22 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get I3C clock frequency. switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { case I3C_SOURCE_HOCO: - SYSTEM_Clocks->I3CCK_Frequency = hoco_frequency; + SYSTEM_Clocks->I3CCLK_Frequency = hoco_frequency; break; case I3C_SOURCE_MOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_8MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_8MHZ; break; case I3C_SOURCE_LOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_XTAL: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_20MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_20MHZ; break; case I3C_SOURCE_SUBCLK: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_PLL: - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); break; default: @@ -651,7 +651,7 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { } // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; // Get futa0 clock frequency. if ( UARTA_SOURCE_LOCO == R_UARTA_CK->UTAnCK[0] & R_UARTA_CK_UTAnCK_CK_Msk ) @@ -870,7 +870,13 @@ static void system_clock_configuration() { R_UARTA_CK->UTAnCK[0] = VALUE_SYSTEM_UTA0CK; R_UARTA_CK->UTAnCK[1] = VALUE_SYSTEM_UTA1CK; + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); // Lock write protection register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; diff --git a/ARM/gcc_clang/system/src/renesas/ra4l1bd3/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra4l1bd3/init_clock.c index 0f03a24a5b..5305cbd205 100644 --- a/ARM/gcc_clang/system/src/renesas/ra4l1bd3/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra4l1bd3/init_clock.c @@ -54,7 +54,7 @@ typedef struct uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz uint32_t UARTA0_Frequency; // FSEL0 clock frequency in Hz uint32_t UARTA1_Frequency; // FSEL1 clock frequency in Hz } SYSTEM_ClocksTypeDef; @@ -626,17 +626,17 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { case I3C_SOURCE_HOCO: - SYSTEM_Clocks->I3CCK_Frequency = hoco_frequency; + SYSTEM_Clocks->I3CCLK_Frequency = hoco_frequency; case I3C_SOURCE_MOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_8MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_8MHZ; case I3C_SOURCE_LOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; case I3C_SOURCE_XTAL: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_20MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_20MHZ; case I3C_SOURCE_SUBCLK: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; case I3C_SOURCE_PLL: - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); default: break; @@ -859,7 +859,13 @@ static void system_clock_configuration() { R_UARTA_CK->UTAnCK[0] = VALUE_SYSTEM_UTA0CK; R_UARTA_CK->UTAnCK[1] = VALUE_SYSTEM_UTA1CK; + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); // Lock write protection register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; diff --git a/ARM/gcc_clang/system/src/renesas/ra4m2/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra4m2/init_clock.c index 8588736f2e..3d1d4ac378 100644 --- a/ARM/gcc_clang/system/src/renesas/ra4m2/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra4m2/init_clock.c @@ -665,6 +665,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra4m3/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra4m3/init_clock.c index fcf148d016..e821d33725 100644 --- a/ARM/gcc_clang/system/src/renesas/ra4m3/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra4m3/init_clock.c @@ -701,6 +701,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra4t1/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra4t1/init_clock.c index 49912677ca..32fe34d3ed 100644 --- a/ARM/gcc_clang/system/src/renesas/ra4t1/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra4t1/init_clock.c @@ -54,7 +54,7 @@ typedef struct uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; @@ -558,22 +558,22 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get I3C clock frequency. switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { case I3C_SOURCE_HOCO: - SYSTEM_Clocks->I3CCK_Frequency = hoco_frequency; + SYSTEM_Clocks->I3CCLK_Frequency = hoco_frequency; break; case I3C_SOURCE_MOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_8MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_8MHZ; break; case I3C_SOURCE_LOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_XTAL: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_20MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_20MHZ; break; case I3C_SOURCE_SUBCLK: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_PLL: - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); break; default: @@ -581,7 +581,7 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { } // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -753,13 +753,19 @@ static void system_clock_configuration() { R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock write protection register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra6e2/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6e2/init_clock.c index e5405b00da..d0a2d0bf50 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6e2/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6e2/init_clock.c @@ -54,7 +54,7 @@ typedef struct uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; @@ -567,22 +567,22 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get I3C clock frequency. switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { case I3C_SOURCE_HOCO: - SYSTEM_Clocks->I3CCK_Frequency = hoco_frequency; + SYSTEM_Clocks->I3CCLK_Frequency = hoco_frequency; break; case I3C_SOURCE_MOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_8MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_8MHZ; break; case I3C_SOURCE_LOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_XTAL: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_20MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_20MHZ; break; case I3C_SOURCE_SUBCLK: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_PLL: - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); break; default: @@ -590,7 +590,7 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { } // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -762,13 +762,19 @@ static void system_clock_configuration() { R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock write protection register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra6m4ad/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m4ad/init_clock.c index 2911a40658..9c8779e854 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m4ad/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m4ad/init_clock.c @@ -746,6 +746,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m4ae/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m4ae/init_clock.c index 2911a40658..9c8779e854 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m4ae/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m4ae/init_clock.c @@ -746,6 +746,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m4af/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m4af/init_clock.c index 2911a40658..9c8779e854 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m4af/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m4af/init_clock.c @@ -746,6 +746,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5_cag/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5_cag/init_clock.c index 08cb15a682..00be679cbb 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5_cag/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5_cag/init_clock.c @@ -767,6 +767,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c index 388240b272..cc5a5894ff 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c @@ -768,6 +768,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c index 388240b272..cc5a5894ff 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c @@ -768,6 +768,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c index 388240b272..cc5a5894ff 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c @@ -768,6 +768,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c index 388240b272..cc5a5894ff 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c @@ -768,6 +768,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c index 388240b272..cc5a5894ff 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c @@ -768,6 +768,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; diff --git a/ARM/gcc_clang/system/src/renesas/ra6t2/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6t2/init_clock.c index 5ee572deb1..28f59b140d 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6t2/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6t2/init_clock.c @@ -54,9 +54,26 @@ typedef struct uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz + uint32_t IICCLK_Frequency; // IIC peripheral clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; +static uint8_t GPT_IIC_CLK_PrescTable[] = { 1, 2, 4, 6, 8 }; + +#define HOCO_FREQUENCY_MHZ_16 (0) +#define HOCO_FREQUENCY_MHZ_18 (1) +#define HOCO_FREQUENCY_MHZ_20 (2) +#define GPT_IIC_SOURCE_HOCO (0) +#define GPT_IIC_SOURCE_MOCO (1) +#define GPT_IIC_SOURCE_LOCO (2) +#define GPT_IIC_SOURCE_MOSC (3) +#define GPT_IIC_SOURCE_PLL (4) +#define GPT_IIC_SOURCE_PLL2 (5) +#define FREQUENCY_32768HZ (32768) +#define FREQUENCY_8MHZ (8000000) +#define FREQUENCY_16MHZ (16000000) +#define FREQUENCY_18MHZ (18000000) +#define FREQUENCY_20MHZ (20000000) /* Key code for writing PRCR register. */ #define BSP_PRV_PRCR_KEY (0xA500U) @@ -554,6 +571,32 @@ static void system_clock_configuration(); // ----------------------------------------------------------------------------------------- +/** + * @brief Gets PLL clock values. + * + * Calculates configured clock frequency for PLL and PLL2. + * + * @return PLL clock value. + */ +uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ + uint32_t hoco_frequency ) { + uint32_t pll_frequency; + + // Get PLL source clock. + if ( pll_config_value & R_SYSTEM_PLLCCR_PLSRCSEL_Msk ) + pll_frequency = hoco_frequency; + else + // Note: MOSC value used by EK-RA6T2 Board. + pll_frequency = FREQUENCY_20MHZ; + // Divide PLL source clock based on PLIDIV value. + pll_frequency /= ( pll_config_value & R_SYSTEM_PLLCCR_PLIDIV_Msk ) + 1; + // Multiply result clock based on PLLMUL value. + pll_frequency *= ( float )(((( pll_config_value & R_SYSTEM_PLLCCR_PLLMUL_Msk )\ + >> R_SYSTEM_PLLCCR_PLLMUL_Pos ) + 1 ) / 2 ); + + return pll_frequency; +} + /** * @brief Gets the system clock values. * @@ -563,7 +606,7 @@ static void system_clock_configuration(); * @return None */ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { - uint32_t prescaler, source_clock; + uint32_t prescaler, source_clock, hoco_frequency; // Get the frequency of main clock. SYSTEM_Clocks->ICLK_Frequency = FOSC_KHZ_VALUE * 1000; @@ -591,6 +634,40 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get FCLK clock frequency. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; SYSTEM_Clocks->FCLK_Frequency = source_clock / prescaler; + + // Get HOCO frequency. + if( HOCO_FREQUENCY_MHZ_16 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 )) + hoco_frequency = FREQUENCY_16MHZ; + else if ( HOCO_FREQUENCY_MHZ_18 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 )) + hoco_frequency = FREQUENCY_18MHZ; + else if ( HOCO_FREQUENCY_MHZ_20 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 )) + hoco_frequency = FREQUENCY_20MHZ; + + // Get IICCLK clock frequency. + switch( VALUE_SYSTEM_IICCKCR & R_SYSTEM_IICCKCR_IICCKSEL_Msk ) { + case GPT_IIC_SOURCE_HOCO: + SYSTEM_Clocks->IICCLK_Frequency = hoco_frequency; + break; + case GPT_IIC_SOURCE_MOCO: + SYSTEM_Clocks->IICCLK_Frequency = FREQUENCY_8MHZ; + break; + case GPT_IIC_SOURCE_LOCO: + SYSTEM_Clocks->IICCLK_Frequency = FREQUENCY_32768HZ; + break; + case GPT_IIC_SOURCE_MOSC: + SYSTEM_Clocks->IICCLK_Frequency = FREQUENCY_20MHZ; + break; + case GPT_IIC_SOURCE_PLL: + SYSTEM_Clocks->IICCLK_Frequency = SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency ); + break; + case GPT_IIC_SOURCE_PLL2: + SYSTEM_Clocks->IICCLK_Frequency = SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency ); + break; + + default: + break; + } + SYSTEM_Clocks->IICCLK_Frequency /= GPT_IIC_CLK_PrescTable[ VALUE_SYSTEM_IICCKDIVCR & R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk ]; } /** @@ -736,6 +813,19 @@ static void system_clock_configuration() { R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped } + if ( !( VALUE_SYSTEM_PLL2CR & R_SYSTEM_PLL2CR_PLL2STP_Msk ) ) { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + R_SYSTEM->PLL2CCR = (uint16_t) VALUE_SYSTEM_PLL2CCR; + R_SYSTEM->PLL2CCR2 = (uint16_t) VALUE_SYSTEM_PLL2CCR2; + R_SYSTEM->PLL2CR_b.PLL2STP = 0; // PLL2 is operating + + while ( !( R_SYSTEM->OSCSF_b.PLL2SF ) ) { + // Wait for PLL2 to stabilize + } + } else { + R_SYSTEM->PLL2CR_b.PLL2STP = 1; // PLL2 is stopped + } + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; @@ -746,9 +836,7 @@ static void system_clock_configuration() { Delay_1ms(); - if ( 80000 < FOSC_KHZ_VALUE && 120000 >= FOSC_KHZ_VALUE ) { - R_FCACHE->FLWT = 2; // 2 waits - } else if ( 40000 < FOSC_KHZ_VALUE ) { + if ( 120000 < FOSC_KHZ_VALUE ) { R_FCACHE->FLWT = 1; // 1 wait } else { R_FCACHE->FLWT = 0; // 0 waits @@ -756,6 +844,14 @@ static void system_clock_configuration() { R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + // Set IICLK parameters + R_SYSTEM->IICCKCR_b.IICCKSREQ = 1; + while ( !( R_SYSTEM->IICCKCR_b.IICCKSRDY )); + R_SYSTEM->IICCKDIVCR = VALUE_SYSTEM_IICCKDIVCR; + R_SYSTEM->IICCKCR = VALUE_SYSTEM_IICCKCR; + R_SYSTEM->IICCKCR_b.IICCKSREQ = 0; + while ( !( R_SYSTEM->IICCKCR_b.IICCKSRDY )); + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out diff --git a/ARM/gcc_clang/system/src/renesas/ra6t3/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6t3/init_clock.c index 9ea0852f15..e6cceb0592 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6t3/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6t3/init_clock.c @@ -54,7 +54,7 @@ typedef struct uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; @@ -560,22 +560,22 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get I3C clock frequency. switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { case I3C_SOURCE_HOCO: - SYSTEM_Clocks->I3CCK_Frequency = hoco_frequency; + SYSTEM_Clocks->I3CCLK_Frequency = hoco_frequency; break; case I3C_SOURCE_MOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_8MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_8MHZ; break; case I3C_SOURCE_LOCO: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_XTAL: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_20MHZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_20MHZ; break; case I3C_SOURCE_SUBCLK: - SYSTEM_Clocks->I3CCK_Frequency = FREQUENCY_32768HZ; + SYSTEM_Clocks->I3CCLK_Frequency = FREQUENCY_32768HZ; break; case I3C_SOURCE_PLL: - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetPLLFrequency( hoco_frequency ); break; default: @@ -583,7 +583,7 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { } // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -755,13 +755,19 @@ static void system_clock_configuration() { R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock write protection register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra8d1/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8d1/init_clock.c index f07ec363aa..10ee4bb3dd 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8d1/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8d1/init_clock.c @@ -57,7 +57,7 @@ typedef struct uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; @@ -842,10 +842,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1063,6 +1063,14 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 0; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1077,8 +1085,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra8d1_dcbd/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8d1_dcbd/init_clock.c index f07ec363aa..10ee4bb3dd 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8d1_dcbd/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8d1_dcbd/init_clock.c @@ -57,7 +57,7 @@ typedef struct uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; @@ -842,10 +842,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1063,6 +1063,14 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 0; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1077,8 +1085,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra8d2a/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8d2a/init_clock.c index 22a87fad0f..28bd0ecf59 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8d2a/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8d2a/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -832,123 +823,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: + case PERIPHERAL_SOURCE_MOSC: // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -993,6 +925,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1027,21 +963,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1349,6 +1285,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1363,8 +1315,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/ra8d2b/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8d2b/init_clock.c index 22a87fad0f..28bd0ecf59 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8d2b/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8d2b/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -832,123 +823,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: + case PERIPHERAL_SOURCE_MOSC: // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -993,6 +925,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1027,21 +963,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1349,6 +1285,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1363,8 +1315,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/ra8m1/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8m1/init_clock.c index 23d92d62a5..1577b8bcc8 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8m1/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8m1/init_clock.c @@ -58,7 +58,7 @@ typedef struct uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; @@ -835,10 +835,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1057,6 +1057,14 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 0; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1071,8 +1079,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra8m2a/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8m2a/init_clock.c index e2260ea117..21078af754 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8m2a/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8m2a/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = {1, 2, 4, 6, 8, 3, 5}; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -815,123 +806,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8M2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -976,6 +908,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1010,21 +946,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1332,6 +1268,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1346,8 +1298,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/ra8t1/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8t1/init_clock.c index b6a0661928..2ac2bceece 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8t1/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8t1/init_clock.c @@ -58,7 +58,7 @@ typedef struct uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; @@ -821,10 +821,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1051,6 +1051,14 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 0; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1065,8 +1073,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra8t1_dcbd/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8t1_dcbd/init_clock.c index b6a0661928..2ac2bceece 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8t1_dcbd/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8t1_dcbd/init_clock.c @@ -58,7 +58,7 @@ typedef struct uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; @@ -821,10 +821,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); + SYSTEM_Clocks->I3CCLK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1051,6 +1051,14 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKREQ = 0; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1065,8 +1073,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; } diff --git a/ARM/gcc_clang/system/src/renesas/ra8t2ad/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8t2ad/init_clock.c index 4b8adedc99..9538a39163 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8t2ad/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8t2ad/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -831,123 +822,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8T2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -992,6 +924,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1026,21 +962,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1348,6 +1284,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1362,8 +1314,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/ra8t2af/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8t2af/init_clock.c index 4b8adedc99..9538a39163 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8t2af/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8t2af/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -831,123 +822,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8T2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -992,6 +924,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1026,21 +962,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1348,6 +1284,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1362,8 +1314,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/ra8t2c/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8t2c/init_clock.c index 4b8adedc99..9538a39163 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8t2c/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8t2c/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -831,123 +822,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8T2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -992,6 +924,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1026,21 +962,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1348,6 +1284,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1362,8 +1314,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/ra8t2j/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8t2j/init_clock.c index 4b8adedc99..9538a39163 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8t2j/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8t2j/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -831,123 +822,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8T2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -992,6 +924,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1026,21 +962,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1348,6 +1284,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1362,8 +1314,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif diff --git a/ARM/gcc_clang/system/src/renesas/ra8t2l/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra8t2l/init_clock.c index 4b8adedc99..9538a39163 100644 --- a/ARM/gcc_clang/system/src/renesas/ra8t2l/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra8t2l/init_clock.c @@ -57,27 +57,27 @@ typedef struct uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t PCLKE_Frequency; // PCLKE clock frequency in Hz uint32_t SPICLK_Frequency; // SPI clock frequency in Hz uint32_t SCICLK_Frequency; // SCI clock frequency in Hz - uint32_t I3CCK_Frequency; // I3C clock frequency in Hz + uint32_t I3CCLK_Frequency; // I3C clock frequency in Hz } SYSTEM_ClocksTypeDef; static uint8_t ClockPrescTable[] = { 1, 2, 4, 8, 16, 32, 64, 0, 3, 6, 12 }; -static uint8_t SCI_SPI_CLK_PrescTable[] = { 1, 2, 4, 6, 8, 3, 5 }; -static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; - -/* Helper macros for getting SPI and SCI clock sources. */ -#define SCI_SPI_SOURCE_HOCO (0) -#define SCI_SPI_SOURCE_MOCO (1) -#define SCI_SPI_SOURCE_LOCO (2) -#define SCI_SPI_SOURCE_MOSC (3) -#define SCI_SPI_SOURCE_SOSC (4) -#define SCI_SPI_SOURCE_PLL1P (5) -#define SCI_SPI_SOURCE_PLL2P (6) -#define SCI_SPI_SOURCE_PLL1Q (7) -#define SCI_SPI_SOURCE_PLL1R (8) -#define SCI_SPI_SOURCE_PLL2Q (9) -#define SCI_SPI_SOURCE_PLL2R (10) +static uint8_t PeriphDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; + +/* Helper macros for getting SPI, SCI, I3C and GPT clock sources. */ +#define PERIPHERAL_SOURCE_HOCO (0) +#define PERIPHERAL_SOURCE_MOCO (1) +#define PERIPHERAL_SOURCE_LOCO (2) +#define PERIPHERAL_SOURCE_MOSC (3) +#define PERIPHERAL_SOURCE_SOSC (4) +#define PERIPHERAL_SOURCE_PLL1P (5) +#define PERIPHERAL_SOURCE_PLL2P (6) +#define PERIPHERAL_SOURCE_PLL1Q (7) +#define PERIPHERAL_SOURCE_PLL1R (8) +#define PERIPHERAL_SOURCE_PLL2Q (9) +#define PERIPHERAL_SOURCE_PLL2R (10) #define HOCO_FREQUENCY_MHZ_16 (0) #define HOCO_FREQUENCY_MHZ_18 (1) #define HOCO_FREQUENCY_MHZ_20 (2) @@ -97,15 +97,6 @@ static uint8_t I3CDividersTable[] = { 1, 2, 4, 6, 8, 3, 5, 10, 16, 32 }; #define PLLMULNF_ONE_THIRD (0x40) #define BSP_PRV_MRCPFB_LIMIT (0x65) -/* Helper macros for getting I3C source clock. */ -#define I3C_SOURCE_MOCO (1) -#define I3C_SOURCE_PLL1P (5) -#define I3C_SOURCE_PLL2P (6) -#define I3C_SOURCE_PLL1Q (7) -#define I3C_SOURCE_PLL1R (8) -#define I3C_SOURCE_PLL2Q (9) -#define I3C_SOURCE_PLL2R (10) - /* Key codes for MRAM registers. */ #define BSP_PRV_MRCFREQ_KEY (0x1E000000) #define BSP_PRV_MREFREQ_KEY (0xE1000000) @@ -831,123 +822,64 @@ uint32_t SYSTEM_GetPLLClocksFrequency( uint32_t pll_config_value, \ } /** - * @brief Gets the peripheral clock values for SPI and SCI modules. + * @brief Gets the peripheral clock values for SPI, SCI, I3C or GPT modules. * - * Calculates configured clock frequency for SPI and SCI clocks. + * Calculates configured clock frequency for SPI, SCI, I3C or GPT clocks. * - * @return SPI or SCI peripheral clock value. + * @return SPI, SCI, I3C or GPT peripheral clock value. */ -uint32_t SYSTEM_GetSPISCIClocksFrequency ( uint8_t config_value, uint32_t hoco_frequency ) { +uint32_t SYSTEM_GetPeriphClocksFrequency( uint8_t config_value, uint32_t hoco_frequency ) { uint32_t peripheral_clock; uint8_t prescaler; switch ( config_value ) { - case SCI_SPI_SOURCE_HOCO: + case PERIPHERAL_SOURCE_HOCO: peripheral_clock = hoco_frequency; break; - case SCI_SPI_SOURCE_MOCO: + case PERIPHERAL_SOURCE_MOCO: peripheral_clock = FREQUENCY_8MHZ; break; - case SCI_SPI_SOURCE_LOCO: + case PERIPHERAL_SOURCE_LOCO: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_MOSC: - // Note: MOSC value used by EK-RA8T2 Board. + case PERIPHERAL_SOURCE_MOSC: + // Note: MOSC value used by EK-RA8D2 Board. peripheral_clock = FREQUENCY_20MHZ; break; - case SCI_SPI_SOURCE_SOSC: + case PERIPHERAL_SOURCE_SOSC: peripheral_clock = FREQUENCY_32768HZ; break; - case SCI_SPI_SOURCE_PLL1P: + case PERIPHERAL_SOURCE_PLL1P: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2P: + case PERIPHERAL_SOURCE_PLL2P: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1Q: + case PERIPHERAL_SOURCE_PLL1Q: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL1R: + case PERIPHERAL_SOURCE_PLL1R: prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2Q: + case PERIPHERAL_SOURCE_PLL2Q: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; peripheral_clock = \ SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); break; - case SCI_SPI_SOURCE_PLL2R: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - - default: - break; - } - - return peripheral_clock; -} - -/** - * @brief Gets the peripheral clock value for I3C module. - * - * Calculates configured clock frequency for I3C clock. - * - * @return I3C peripheral clock value. - */ -uint32_t SYSTEM_GetI3CClockFrequency ( uint32_t hoco_frequency ) { - uint32_t peripheral_clock; - uint8_t prescaler; - - switch ( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk ) { - case I3C_SOURCE_MOCO: - peripheral_clock = FREQUENCY_8MHZ; - break; - case I3C_SOURCE_PLL1P: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVP_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2P: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1Q: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVQ_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL1R: - prescaler = (( VALUE_SYSTEM_PLLCCR2 & R_SYSTEM_PLLCCR2_PLODIVR_Msk ) \ - >> R_SYSTEM_PLLCCR2_PLODIVR_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLLCCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2Q: - prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk ) \ - >> R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos ) + 1; - peripheral_clock = \ - SYSTEM_GetPLLClocksFrequency( VALUE_SYSTEM_PLL2CCR, hoco_frequency, prescaler ); - break; - case I3C_SOURCE_PLL2R: + case PERIPHERAL_SOURCE_PLL2R: prescaler = (( VALUE_SYSTEM_PLL2CCR2 & R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk ) \ >> R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos ) + 1; peripheral_clock = \ @@ -992,6 +924,10 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF0000000 ) >> 28 ]; SYSTEM_Clocks->MRPCLK_Frequency = source_clock / prescaler; + // Get PCLKE clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF00000 ) >> 20 ]; + SYSTEM_Clocks->PCLKE_Frequency = source_clock / prescaler; + // Get the frequency of system clock. prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0xF000000 ) >> 24 ]; SYSTEM_Clocks->ICLK_Frequency = source_clock / prescaler; @@ -1026,21 +962,21 @@ void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { // Get the source clock of SPI module. SYSTEM_Clocks->SPICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SPICKCR & R_SYSTEM_SPICKCR_CKSEL_Msk, hoco_frequency ); // Adjust SPICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SPICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SPICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SPICKDIVCR & R_SYSTEM_SPICKDIVCR_CKDIV_Msk ]; // Get the source clock of SCI module. SYSTEM_Clocks->SCICLK_Frequency = \ - SYSTEM_GetSPISCIClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_SCICKCR & R_SYSTEM_SCICKCR_SCICKSEL_Msk, hoco_frequency ); // Adjust SCICLK based on the SPICKDIVCR value. - SYSTEM_Clocks->SCICLK_Frequency /= SCI_SPI_CLK_PrescTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; + SYSTEM_Clocks->SCICLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_SCICKDIVCR & R_SYSTEM_SCICKDIVCR_CKDIV_Msk ]; // Get I3C clock frequency. - SYSTEM_Clocks->I3CCK_Frequency = SYSTEM_GetI3CClockFrequency( hoco_frequency ); - - // Get I3C clock with requested divider. - SYSTEM_Clocks->I3CCK_Frequency /= I3CDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; + SYSTEM_Clocks->I3CCLK_Frequency = \ + SYSTEM_GetPeriphClocksFrequency( VALUE_SYSTEM_I3CCKCR & R_SYSTEM_I3CCKCR_I3CCKSEL_Msk, hoco_frequency ); + // Adjust I3CCLK based on the I3CCKDIVCR value. + SYSTEM_Clocks->I3CCLK_Frequency /= PeriphDividersTable[ VALUE_SYSTEM_I3CCKDIVCR & R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk ]; } /** @@ -1348,6 +1284,22 @@ static void system_clock_configuration() { R_SYSTEM->SCICKCR_b.CKSREQ = 0; while ( R_SYSTEM->SCICKCR_b.CKSRDY ); + // Set I3CCLK parameters + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 1; + while ( !( R_SYSTEM->I3CCKCR_b.I3CCKSRDY )); + R_SYSTEM->I3CCKDIVCR = VALUE_SYSTEM_I3CCKDIVCR; + R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; + R_SYSTEM->I3CCKCR_b.I3CCKSREQ = 0; + while ( R_SYSTEM->I3CCKCR_b.I3CCKSRDY ); + + // Set ADCCLK parameters + R_SYSTEM->ADCCKCR_b.CKSREQ = 1; + while ( !( R_SYSTEM->ADCCKCR_b.CKSRDY )); + R_SYSTEM->ADCCKDIVCR = VALUE_SYSTEM_ADCCKDIVCR; + R_SYSTEM->ADCCKCR = VALUE_SYSTEM_ADCCKCR; + R_SYSTEM->ADCCKCR_b.CKSREQ = 0; + while ( R_SYSTEM->ADCCKCR_b.CKSRDY ); + /* If PLL2 is enabled and PLL1 is not chosen as source clock * or PLL2 is disabled and PLL1 is chosen as clock source. */ @@ -1362,8 +1314,6 @@ static void system_clock_configuration() { R_SYSTEM->LVOCR = 0; } - R_SYSTEM->I3CCKCR = VALUE_SYSTEM_I3CCKCR; - // Lock LVOCR register R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #endif