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<!DOCTYPE HTML>
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<a href="index.html" class="logo"><strong>Edu4Chip</strong> - Joint Education for Advanced Chip Design in Europe</a>
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<li>
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<!-- Content -->
<section>
<!--header class="main">
<h2>Edu4Chip Summer School 2025 on Chip Design</h2>
</header-->
<!-- Descriptions -->
<!--h2 id="content">
Summary
</h2-->
<h1 id="overview" style="margin-top: -0.75em;">Overview</h1>
<p>
<figure class="image right">
<img src="images/summer_25/copenhagen.jpg" alt=""/>
<figcaption style="font-size: 0.8em; text-align: right;">Photo credit: Luca Pezzarossa.</figcaption>
</figure>
Welcome to the <strong>Edu4Chip Summer School 2025 on Chip Design</strong>. The summer school offers an introduction to the chip design process from specification to testing including the use of open-source tool chains.
</p>
<p>
The summer school is organized by the <strong>Technical University of Denmark (DTU)</strong> in collaboration with <strong>Edu4Chip partner institutions</strong> and will take place in <strong>Denmark</strong> at the <strong>Technical University of Denmark campus in Kongens Lyngby</strong> (near Copenhagen).
</p>
<p>
The summer school is structured into two main parts:
<ul>
<li><strong>Online intro-day (August 11th)</strong> - Covering fundamental concepts in chip and digital design, with interactive exercises and project introductions.</li>
<li><strong>In-person program (August 18th to 22nd)</strong> - Held at DTU in Denmark, featuring in-depth lectures, hands-on activities, keynotes, and social events.</li>
</ul>
</p>
<h4>Target audience and scope</h4>
<p>
The summer school is designed for <strong>Bachelor students</strong> and <strong>Master students</strong> with a background in electrical engineering, computer science and engineering, or physics, the summer school emphasizes practical learning activities. <strong>PhD students</strong> are also welcome. Participants will acquire <strong>foundational knowledge of chip design workflows, develop skills in tools and methodologies, and explore cutting-edge developments in the field</strong>.
</p>
<h4>ECTS credit transfer and financial support</h4>
<p>
The Edu4Chip Summer School is organized within the framework of the <strong>Erasmus Blended Intensive Program (BIP)</strong>, which allows for <strong>credit transfer</strong> among participating institutions. Upon successful completion within the BIP, students can be awarded <strong>3 ECTS credits</strong>. For students enrolled at <strong>DTU</strong>, the summer school can be integrated into a more extensive <strong>3-week special course</strong>, allowing them to earn <strong>5 ECTS credits</strong>.
</p>
<p>
For details on financial support options, especially for students from Erasmus partner institutions and Edu4Chip partners, please refer to the <strong><a href="#financial-support">Financial Support</a></strong> section.
</p>
<h4>Additional sponsorship</h4>
<p style="margin-bottom: 0.5em; padding-bottom: 0em">
In addition to the EU financial support the summer school is co-sponsored by the <strong><a href="https://chips-competence-centre.dtu.dk/en/" target="_blank">Danish Chip Competence Center</a></strong>.
</p>
<div style="display: flex; flex-direction: row; align-items: center; flex-wrap: wrap; margin-top: 0em; padding-top: 0em">
<div>
<span class="image" style="margin-right: 2em; padding-top: 0em; padding-bottom: 0.5em"><img src="images/summer_25/dkccc_logo.jpg" alt="" style="width: 180px;"></span>
</div>
</div>
<!--p>
<strong>Find all the information you need about the summer school on this page.</strong> The content is organized into sections that cover, pre-registration details, financial support options, and the program.
Scroll or use the <strong>side menu</strong> to navigate through the different sections.
</p-->
<!--h2 id="content">Contents</h2>
<ul>
<li><a href="#pre-registration">Pre-registration</a></li>
<li><a href="#financial-support">Financial support</a></li>
<li><a href="#program-and-content">Program and content</a>
<li><a href="#questions-and-contacts">Questions and contacts</a></li>
</ul-->
<hr>
<h1 id="practical_information">Practical information</h1>
<p>
Please find below some practial information realted to location, accomodation, and transport.
</p>
<h2>Location</h2>
<p>
The Edu4Chip Summer School will take place at the Technical University of Denmark (DTU) in Kongens Lyngby, a town located just north of Copenhagen.
</p>
<ul>
<li><strong>Venue:</strong> Technical University of Denmark Meeting Center, Building 101, Room S09</li>
<li><strong>Address:</strong> Anker Engelunds Vej 1, 2800 Kongens Lyngby</li>
<li><strong>Google Maps link:</strong> <a href="https://maps.app.goo.gl/jrppyPdLtKVFieE28" target="_blank">View location</a></li>
</ul>
<p>
To help you get oriented, here is a map showing the location of DTU in Kongens Lyngby. This should give you a better sense of the surrounding area and help you plan your accommodation and travel accordingly.
</p>
<span class="image main"><img src="images/summer_25/summer25_map_1.jpg" alt="" /></span>
<h2 id="accommodation">Accommodation</h2>
<p>
DTU does not offer on-campus accommodation for summer school participants. Each student is responsible for arranging their own accommodation independently.
We recommend searching through popular platforms such as Booking.com, Airbnb, or similar services to find lodging that fits your preferences and budget.
</p>
<p>
You may choose to stay near the university in Kongens Lyngby for convenience, or in Copenhagen if you prefer a more urban environment. <strong>Important:</strong> In general public transport is feasable from either location. However, before booking your accommodation, we recommend checking public transport routes to and from DTU. Some places that appear geographically close to the university may not be conveniently connected by public transport. See the next section for more information about transport options.
</p>
<h2 id="transport">Transport</h2>
<p>
If you're arriving from abroad, the nearest airport is <strong>Copenhagen Airport (CPH)</strong>, which is well-connected to the city center by the Metro. The journey from the airport to central Copenhagen typically takes around 15-20 minutes.
</p>
<p>
The summer school venue in Kongens Lyngby is connected to Copenhagen via the <strong>S-train (commuter train)</strong> and several bus lines. The commute from central Copenhagen to Lyngby takes approximately 30 minutes. Public transport in the Greater Copenhagen area is reliable, safe, and frequent.
</p>
<p>
We suggest using tools such as <a href="https://www.google.com/maps" target="_blank">Google Maps</a> or <a href="https://www.rejseplanen.dk/" target="_blank">Rejseplanen.dk</a> to explore travel options and find the best routes and timetables.
</p>
<p>
A map of the train lines and information about tickets and fares is also available at <a href="https://www.dsb.dk/en/travelling-in-the-cities/copenhagen/" target="_blank">DSB's official website</a>.
</p>
<h2 id="tips">Useful tips</h2>
<p>
<strong>Bring your laptop and charger:</strong> You will need a laptop for the summer shcool program. Denmark uses Type C or K plugs (EU standard, 230 V), check if you need an adapter.
</p>
<p>
<strong>Dress smart for unpredictable weather:</strong> Copenhagen summer temperatures can range from 10°C to 28°C. Bring different layers (T-shirts, sweaters, a light jacket) to adapt easily throughout the day. Pack a small umbrella or a waterproof jacket, and consider water-resistant shoes or quick-drying clothing.
</p>
<p>
<strong>Other handy items:</strong> Sunscreen (hopefully we might need it!), and a notebook/pen for quick notes and drafts.
</p>
<hr>
<h1 id="program-and-content">Program and content</h1>
<p>
Over six days, including the online introductory day, participants will engage in lectures, hands-on exercises, and keynotes delivered by leading academics and industry experts. The program highlights topics such as agile hardware design, analog/mixed-signal circuits, verification techniques, and asynchronous circuits.
</p>
<p>
The Edu4Chip Summer School is structured into two main parts: an <strong>Online intro-day</strong> and an <strong>In-person program</strong> in Copenhagen.
Find below the schedule, and a detailed description of the content of the online intro-day, in-person lectures, keynotes, and other activities, as well as the learning objectives.
</p>
<h2 id="content">Schedule</h2>
<span class="image main"><img src="images/summer_25/summer2025_program_v8.jpg" alt="" /></span>
<div class="schedule-table">
<div class="schedule-column-1">
<h3 style="margin-bottom: 0em;">Online intro-day - Monday, August 11th</h3>
<i>Teacher for the day: Assoc. Prof. Luca Pezzarossa (Technical University of Denmark)</i>
<h4 style="margin-bottom: 0.5em; margin-top: 0.5em;">09:30 - 12:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Welcome</li>
<li>Introduction to the summer school</li>
<li>Q&A and discussion session</li>
<li>Participant attendance check-in</li>
<li>Brush-up on Digital Design</li>
</ul>
<h4 style="margin-bottom: 0.5em;">12:00 - 13:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 1em;">
<li>Lunch break</li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:00 - 14:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Brush-up on Digital Design (continues)</li>
</ul>
<h4 style="margin-bottom: 0.5em;">14:00 - 16:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Exercises</li>
</ul>
<h4 style="margin-bottom: 0.5em;">16:00 - 16:30</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Outline of the student project</li>
<li>Participant attendance check-out</li>
</ul>
<h4 style="margin-bottom: 0.5em;">16:30 - 17:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Q&A and discussion session</li>
</ul>
</div>
<div class="schedule-column-2">
<h3>In-person day 1 - Monday, August 18th</h3>
<h4 style="margin-bottom: 0.5em;">10:00 - 10:15</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Registration and coffee/breakfast</li>
</ul>
<h4 style="margin-bottom: 0.5em;">10:15 - 11:10</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Welcome from the organizers</li>
<li>Summer school introduction and overview</li>
<li>Welcome message from Prof. Jan Madsen, Head of Department at DTU Compute</li>
</ul>
<h4 style="margin-bottom: 0.5em;">11:10 - 12:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Presentation: <strong>A Nordic and European perspective on chips</strong>, by Claus Friis Pedersen (Danish Chip Competence Center) and Lars Palm (Swedish Chip Competence Center)</li>
</ul>
<h4 style="margin-bottom: 0.5em;">12:00 - 13:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lunch served at the summer school location</li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:00 - 13:50</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Keynote: <strong>From the 1st transistor to FinFETs</strong>, and beyond, by Assoc. Prof. Flemming Stassen (Technical University of Denmark)</li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:50 - 14:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Break</li>
</ul>
<h4 style="margin-bottom: 0.5em;">14:00 - 15:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Presentation: <strong>The Edu4Chip project</strong>, by Edu4Chip partners</li>
</ul>
<h4 style="margin-bottom: 0.5em;">15:00 - 15:15</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Break: Coffee and refreshments</li>
</ul>
<h4 style="margin-bottom: 0.5em;">15:15 - 17:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lecture: <strong>Chip design process overview</strong>, by Univ. Instuctor Arto Oinonen and Doctoral Researcher Matti Käyrä (Tampere University)</li>
</ul>
<h4 style="margin-bottom: 0.5em;">17:00 - 18:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Quickfire introduction of students</li>
</ul>
</div>
</div>
<div class="schedule-table">
<div class="schedule-column-1">
<h3>In-person day 2 - Tuesday, August 19th</h3>
<h4 style="margin-bottom: 0.5em;">09:00 - 12:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lecture & hands-on session: <strong>Agile hardware design in HDL</strong>, by Prof. Martin Schoeberl (Technical University of Denmark)</li>
<li>Break for coffee and refreshments at 10:30</li>
</ul>
<h4 style="margin-bottom: 0.5em;">12:00 - 13:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lunch at the kantine in Building 202. <strong>Google Maps link:</strong> <a href="https://maps.app.goo.gl/2pbpsBjFdY5amgXo9" target="_blank">View location</a></li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:00 - 13:50</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Keynote: <strong>Design for low-power ICs for hearing instruments</strong>, by Evangelia Kasapaki and Vijay Kumar Bhat (Demant)</li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:50 - 14:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Break</li>
</ul>
<h4 style="margin-bottom: 0.5em;">14:00 - 17:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lecture & hands-on session: <strong>Systems-on-chip and interconnects</strong>, by Assoc. Prof. Luca Pezzarossa (Technical University of Denmark)</li>
<li>Break for coffee and refreshments at 15:00</li>
</ul>
<h4 style="margin-bottom: 0.5em;">17:10 - 19:30</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Picnic on DTU premises</li>
<li>Location: Wicked Rabbit Kantine in Building 342. <strong>Google Maps link:</strong> <a href="https://maps.app.goo.gl/iKtAkE2Es2kXks3R6" target="_blank">View location</a></li>
</ul>
</div>
<div class="schedule-column-2">
<h3>In-person day 3 - Wednesday, August 20th</h3>
<h4 style="margin-bottom: 0.5em;">09:00 - 12:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lecture & hands-on session: <strong>Time-discrete analog circuits</strong>, by Dipl.-Ing. (Univ.) Markus Dietl (Technical University of Munich)</li>
<li>Break for coffee and refreshments at 10:30</li>
</ul>
<h4 style="margin-bottom: 0.5em;">12:00 - 13:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lunch served at the summer school location</li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:00 - 16:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lecture & hands-on session: <strong>Verification of digital circuits</strong>, by Jacob Sander Andersen (Syosil)</li>
<li>Break for coffee and refreshments at 14:30</li>
</ul>
<h4 style="margin-bottom: 0.5em;">16:00 - 19:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Walking tour of Copenhagen (bring an umbrella!)</li>
<li>Bus to Copenhagen <strong>departs at 16:10 from outside Building 101</strong> (summer school location)</li>
</ul>
<h4 style="margin-bottom: 0.5em;">19:00 - 20:45</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Dinner in Copenhagen</li>
<li>Location: Restaurant Sult i Cinemateket, Vognmagergade 8B, 1120 København K. <strong>Google Maps link:</strong> <a href="https://maps.app.goo.gl/GLHnZgnss3ZhzjYb9" target="_blank">View location</a></li>
</ul>
</div>
</div>
<div class="schedule-table" style="margin-bottom: 1.5em;">
<div class="schedule-column-1" style="border-bottom: 0px">
<h3>In-person day 4 - Thursday, August 21st</h3>
<h4 style="margin-bottom: 0.5em;">09:00 - 12:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lecture & hands-on session: <strong>Chip design process and challenges</strong>, by Assist. Prof. Ole Richter (Technical University of Denmark)</li>
<li>Break for coffee and refreshments at 10:30</li>
</ul>
<h4 style="margin-bottom: 0.5em;">12:00 - 13:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lunch at the kantine in Building 202. <strong>Google Maps link:</strong> <a href="https://maps.app.goo.gl/2pbpsBjFdY5amgXo9" target="_blank">View location</a></li></li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:00 - 13:50</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Keynote: <strong>"Basic concepts in modeling" - A discussion of George Box's famous statement 'All models are wrong, some are useful' with a strong focus on models in chip design</strong>, by Prof. Dr.-Ing. Wolfgang Ecker (Infineon / Technical University of Munich)</li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:50 - 14:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Break</li>
</ul>
<h4 style="margin-bottom: 0.5em;">14:00 - 17:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lecture - advanced topics: <strong>Asynchronous circuits</strong>, by Emeritus Prof. Jens Sparsø (Technical University of Denmark)</li>
<li>Lecture - advanced topics: <strong>Formal verification</strong>, by Prof. Oliver Keszöcze (Clausthal University of Technology)</li>
<li>Lecture - advanced topics: <strong>LEGO inspired chip design</strong>, by Prof. Ahmed Hemani (KTH Royal Institute of Technology)</li>
<li>Break for coffee and refreshments at 15:00</li>
</ul>
<h4 style="margin-bottom: 0.5em;">17:00 - 19:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Project work (preparation of the student presentations)</li>
</ul>
</div>
<div class="schedule-column-2" style="border-bottom: 0px">
<h3>In-person day 5 - Friday, August 22nd</h3>
<h4 style="margin-bottom: 0.5em;">09:00 - 12:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Student presentations (count as exam)</li>
<li>Coffee and refreshments at 09:00</li>
</ul>
<h4 style="margin-bottom: 0.5em;">12:00 - 13:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Lunch served at the summer school location</li>
</ul>
<h4 style="margin-bottom: 0.5em;">13:00 - 14:00</h4>
<ul style="margin-left: 1.5em; margin-bottom: 0.75em;">
<li>Summer school wrap-up</li>
<li>Farewell</li>
</ul>
</div>
</div>
<h2 id="content">Content of the online intro-day (August 11th)</h2>
<p>
The online into-day provides an overview of the Edu4Chip Summer School, covering fundamental concepts in chip and digital design. Participants will engage in interactive exercises and receive guidance on the student project to prepare for the in-person sessions. Find below a summary of the intro-day activities.
</p>
<ul>
<li>
<strong>Introduction to the summer school</strong>
<br>
An overview of the summer school, its objectives, and an introduction to the program, participants, and instructors.
</li>
<li style="margin-top: 1em;">
<strong>Brush-up on digital design</strong>
<br>
A refresher session focusing on essential digital design concepts to ensure all participants are aligned with the foundational knowledge.
</li>
<li style="margin-top: 1em;">
<strong>Interactive web-based exercises</strong>
<br>
Hands-on activities where participants will design and simulate an integrated circuit using open-source tools.
</li>
<li style="margin-top: 1em;">
<strong>Outline of the student project</strong>
<br>
Introduction to the student project, detailing objectives and expected outcomes. Projects will be carried out during the summer school.
</li>
<li style="margin-top: 1em;">
<strong>Q&A and discussion session</strong>
<br>
An interactive session for participants to engage with instructors, ask questions, and discuss key topics covered throughout the day and planned for the physical part of the summer school.
</li>
</ul>
<h2 id="content">Content of the in-person program (August 18th to 22nd)</h2>
<p>
The in-person program offers a blend of keynotes, lectures, and hands-on activities. In addition to the lectures and keynotes, we also planned some activities to connect, relax, and explore both the academic environment and the vibe of Copenhagen. Find the details below.
</p>
<h3 id="content">Presentations and keynotes</h3>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/claus_friis_pedersen.jpg" alt="" style="margin-right: 0.5em; width:75px;"/>
<img src="images/summer_25/lars_palm.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>A Nordic and European perspective on chips</strong>
<br>
<i>by Claus Friis Pedersen (Danish Chip Competence Center) and Lars Palm (Swedish Chip Competence Center)</i>
</div>
<div style="float: inline-end;">
This opening presentation gives an introduction to the new opportunities emerging within the European chips eco-system chip as a result of increased European focus and cooperation, e.g. within the framework of the Chips Joint Undertaking (ChipsJU). The key elements of ChipsJu such as Pilotlines, Design Tool and Chips Competence Centers will be introduced. The presentation will then focus on how this is implemented in the Nordic countries and the specific opportunities this can provide to companies, academia, employees and students who are active in the chips area.
<br><br>
<strong>Claus Friis Pedersen</strong> is heading the Danish Chips Competence Centre. He has a back-ground in commercial deep-tech and business development in various industries including Photonics, Renewable energy, and Chips for Quantum Information processing.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/michael_pehl.jpg" alt="" style="margin-right: 0.5em; width:75px;"/>
<img src="images/summer_25/extra.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>The Edu4Chip project</strong>
<br>
<i>by Dr.-Ing. habil. Michael Pehl (Technical University of Munich), Univ. Instuctor Arto Oinonen (Tampere University), Prof. Jean-Max Dutertre (Institut Mines-Télécom), Prof. Ahmed Hemani (KTH Royal Institute of Technology), and Assoc. Prof. Matthias Bo Stuart (Technical University of Denmark DTU)</i>
</div>
<div style="float: inline-end;">
The presentation will highlight the structure and objectives of the project, including joint courses offered at the partner institutions, opportunities for student exchange, and the possibility of pursuing Master's thesis projects within the Edu4Chip framework.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/flemming_stassen.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>From the 1st transistor, to FinFETs, and beyond</strong>
<br>
<i>by Assoc. Prof. Flemming Stassen, Technical University of Denmark</i>
</div>
<div style="float: inline-end;">
This keynote will introduce the audience on a historical and technical journey through transistor evolution. Beginning with the pioneering transistor prototypes that launched the semiconductor revolution, the talk will present the architecture and scaling challenges of planar MOS devices. It will then transition to modern FinFET technology, unpacking its advantages in leakage control, performance, and scaling into the nanometer era. Finally, the presentation will explore newer and future approaches, such as gate-all-around transistors.
<br><br>
<strong>Flemming Stassen</strong> is an Associate Professor at Technical University of Denmark, where he carries out teaching in Digital Electronics, VLSI Design, and Test of Digital Systems. His long-standing teaching record and recognized excellence (DTU Faculty of the Year, 2001) reflect his passion for educating the next generation of chip designers.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/evangelia_kasapaki.jpg" alt="" style="margin-right: 0.5em; width:75px;"/>
<img src="images/summer_25/vijay_kumar_bhat.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Design for low-power ICs for hearing instruments</strong>
<br>
<i>by Evangelia Kasapaki and Vijay Kumar Bhat, from the company Demant</i>
</div>
<div style="float: inline-end;">
The keynote presents and discusses hardware strategies for supporting hearing instruments applications like audio processing, AI, and wireless communication on a constrained power budget.
Advanced hearing aids use integrated circuits (ICs) characterized by critical requirements of PPA: Power (power efficiency), Performance (throughput, latency, signal quality), and area (IC area, RAM, ROM, NVRAM). On the other hand, the hearing instruments need to handle diverse applications like audiology and wireless protocols. Thus, the hearing instruments ICs rely on high level of specialization in IC technology, digital-analog circuits, micro-controllers, DSP, and AI processors. Overall, the hearing instruments consist of multiple specialized ICs and within the ICs can be multiple processor cores, all these are tied together with performant yet efficient communication busses and NOC.
<br><br>
<strong>Evangelia Kasapaki</strong> and <strong>Vijay Kumar Bhat</strong> are industry experts working at Demant, a leading company in hearing aid technology. They have extensive experience in the design and development of low-power integrated circuits for hearing instruments.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/wolfgang_ecker.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>"Basic concepts in modeling" - A discussion of George Box's famous statement 'All models are wrong, some are useful' with a strong focus on models in chip design</strong>
<br>
<i>by Prof. Dr.-Ing. Wolfgang Ecker, Infineon - Technical University of Munich</i>
</div>
<div style="float: inline-end;">
The keynote covers guiding principles of models and elaborates that the most important feature of a model is abstraction. It discusses different digital design abstraction methods — others say disciplines — as Lumped Model, Value Discrete Models and Time Discrete Models. It also relates these abstractions to pre-clustered elements as Transistors, Gates as well as Registers and Transfer Functions. The talk further discusses similarities between the abstraction levels and relates them to current IP-based design. All through the talk George Box’s famous statement is reflected. Situations and challenges are brought up, especially what happens if models are becoming reality.
<br><br>
<strong>Wolfgang Ecker</strong> is a Distinguished Engineer at Infineon and Professor at Technical University of Munich. His research and innovation focus lie on digital system modeling, digital design automation, SoC architectures, embedded AI and AI for design automation. He published over 200 papers, received six publication awards and has been granted with the German EDA achievement award. He is member of Acatech, the German Academy of Science and Engineering and has been member of the AI commission of inquiry of the German Government.
</div>
</td>
</tr>
</tbody>
</table>
<h3 id="content">Lectures</h3>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/arto_oinonen.jpg" alt="" style="margin-right: 0.5em; width:75px;"/>
<img src="images/summer_25/matti_kayra.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Chip design process overview</strong>
<br>
<i>by Univ. Instuctor Arto Oinonen and Doctoral Researcher Matti Käyrä, Tampere University</i>
</div>
<div style="float: inline-end;">
This lecture provides an introductory overview of the chip design process, covering key steps from initial specification and architecture design to RTL development, verification, synthesis, physical design, fabrication, and final testing of the chip. The lecture covers also the design process including project management, scheduling as well as developer roles and expertise and overall resourcing. We use real System-on-Chip designs from sochub.fi as use cases and takeouts.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/martin_schoeberl.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Agile hardware design in HDL</strong>
<br>
<i>by Prof. Martin Schoeberl, Technical University of Denmark</i>
</div>
<div style="float: inline-end;">
The lecture on Agile hardware design with Chisel (Constructing Hardware in a Scala Embedded Language) focuses on using the Chisel hardware construction language as part of the agile hardware design process. Chisel is a modern hardware description language that enables designers to create digital circuits with concise, high-level code that is easier to write and maintain than traditional HDLs.
<br><br>
Agile hardware design applies modern software development methods to the design of hardware. With functional programming in Scala, you will learn how to write so-called hardware generators. This lecture includes hands-on describing a generator In Chisel.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/luca_pezzarossa.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Systems-on-chip and interconnects</strong>
<br>
<i>by Assoc. Prof. Luca Pezzarossa, Technical University of Denmark</i>
</div>
<div style="float: inline-end;">
This lecture provides an introduction to system-on-chip (SoC) architectures and interconnect technologies, essential for modern chip design. SoCs integrate multiple components such as processors, memories, accelerators, and peripherals into a single chip, enabling high-performance and energy-efficient computing. The lecture examines the challenges of designing scalable and flexible SoCs, focusing on SoC design principles and how different interconnect strategies (traditional bus-based communication, AXI4Lite, and advanced Networks-on-Chip (NoC) solutions) impact the design performance, power consumption, and modularity.
<br><br>
The lecture includes a hands-on laboratory session, where students explore the use of NoC based interconnect architectures in a multicore setting.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/markus_dietl.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Time-discrete analog circuits</strong>
<br>
<i>by Dipl.-Ing. (Univ.) Markus Dietl, Technical University of Munich</i>
</div>
<div style="float: inline-end;">
The lecture covers the basics of time discrete circuits. Clocked analogue circuits are used very frequently in modern integrated circuit technology. There are inherently discrete-time circuits and those that convert an actually continuous variable (such as voltage) into a discrete-time variable by sampling, clocked charging or averaging.
<br><br>
Analogue-to-digital converters (ADCs) are an example of discrete-time circuits that convert the continuous variable of voltage into a discrete-time variable by sampling. DC-DC converters map a continuous voltage to another continuous voltage, but the conversion process utilises a clocked process. These converters therefore utilise a discrete-time control loop. Phase-locked loops (PLLs) generate frequencies and measure the time interval between two edges. They are therefore inherently discrete-time circuits. Both frequency and phase are discrete-time quantities. The lecture explains the difference to time continuous circuits, and how to model and design time discrete systems.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/ole_richter.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Chip design process and challenges</strong>
<br>
<i>by Assist. Prof. Ole Richter, Technical University of Denmark</i>
</div>
<div style="float: inline-end;">
In this lesson, we will walk through a small example of chip design, starting from a netlist to a real Application Specific Integrated Circuit (ASIC) design ready for fabrication. We will go through timing, placement, routing, and physical verification using publicly available tools. This presentation will give you a hands-on look at the potential challenges you may face in future projects and how to overcome them. We will examine the individual steps in timing, placement, routing, and physical verification and gain a deeper understanding of what is happening.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/jacob_sander_andersen.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Verification of digital circuits</strong>
<br>
<i>by Jacob Sander Andersen, from the company Syosil</i>
</div>
<div style="float: inline-end;">
This lecture, delivered by experts from Syosil, a Danish company specializing in verification solutions, covers the verification of digital circuits, focusing on methodologies and tools used to ensure design correctness (simulation, formal verification, etc.).
<br><br>
The lecture will cover some basic theory on functional verification and highlight some of the problems attached to the field, predominately explained through simulation based functional verification. A demo of formal verification will be given and lastly some small exercises involving constrained random verification will be conducted.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/jens_sparsoe.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Advanced topics: Asynchronous Circuits</strong>
<br>
<i>by Emeritus Prof. Jens Sparsø, Technical University of Denmark</i>
</div>
<div style="float: inline-end;">
This lecture introduces asynchronous circuits, which are digital circuits that operate without a global clock. Unlike synchronous circuits, which rely on a central clock signal to coordinate operations, asynchronous circuits use local handshaking and data-driven control mechanisms. This class of circuits can lead to advantages in terms of power efficiency, performance, and robustness compared to traditional synchronous designs.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/oliver_keszocze.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Advanced topics: Formal verification</strong>
<br>
<i>by Prof. Oliver Keszöcze, Clausthal University of Technology</i>
</div>
<div style="float: inline-end;">
This lecture introduces hardware verification, comparing traditional testing with formal methods. We'll start by modeling digital circuits mathematically, laying the groundwork for understanding formal verification's rigorous approach. We'll explore how formal techniques, unlike testing, offer mathematical guarantees of correctness.
<br><br>
Building on that foundation, we will focus on the yopic of equivalence checking, which verifies that circuit designs are functionally identical. We'll discuss why this is a question of practical importance and learn methods for actually carrying out the equivalence test.
</div>
</td>
</tr>
</tbody>
</table>
<table>
<tbody>
<tr>
<td>
<div style="float: left;">
<img src="images/summer_25/ahmed_hemani.jpg" alt="" style="margin-right: 1em; width:75px;"/>
</div>
<div style="float: none;">
<strong>Advanced topics: LEGO-inspired chip design</strong>
<br>
<i>by Prof. Ahmed Hemani, KTH Royal Institute of Technology</i>
</div>
<div style="float: inline-end;">
Computer architects and the design automation community pursue efficiency improvements across multiple dimensions: computation, silicon, design, and manufacturing. However, state-of-the-art standard cell-based tooling has become unscalable, even as the demand for higher performance and computational efficiency continues to rise. To address these challenges, a Lego-inspired design framework called SiLago has been developed, demonstrating promising results—achieving 10 to 100 times better energy efficiency compared to COTS solutions. SiLago enables end-to-end automation while delivering ASIC-comparable efficiency. The generated designs are correct by construction, as well as timing and DRC-clean. Furthermore, SiLago is being explored beyond CMOS technologies, including applications in memristor-based computation and wave-based computing.
</div>
</td>
</tr>
</tbody>
</table>
<h3 id="content">Other activities</h3>
<ul>
<li>
<strong>Quickfire introduction of students</strong>
<br>
A fast-paced session where participants briefly introduce themselves to get to know each other.
</li>
<li style="margin-top: 1em;">
<strong>Student presentations (counts as the exam)</strong>
<br>
An interactive presentation session where students present their project outcomes, followed by an evaluation to conclude the summer school.
</li>
<li style="margin-top: 1em;">
<strong>Walking tour of Copenhagen (bring an umbrella!)</strong>
<br>
A tour to provide participants with an opportunity to explore the city’s vibe and architecture.
Bus to Copenhagen <strong>departs at 16:10 from outside Building 101</strong> (summer school location).
</li>
<li style="margin-top: 1em;">
<strong>Picnic on DTU premises</strong>
<br>
A welcome picnic on DTU premises. Location: Wicked Rabbit Kantine in Building 342. <strong>Google Maps link:</strong> <a href="https://maps.app.goo.gl/iKtAkE2Es2kXks3R6" target="_blank">View location</a>
</li>
<!--li style="margin-top: 1em;">
<strong>Jogging route on DTU campus</strong>
<br>
A casual group jogging session around the DTU campus.
</li-->
<li style="margin-top: 1em;">
<strong>Social dinner in Copenhagen</strong>
<br>
A social dinner in Copenhagen open to all the participants. Location: Restaurant Sult i Cinemateket, Vognmagergade 8B, 1120 København K. <strong>Google Maps link:</strong> <a href="https://maps.app.goo.gl/GLHnZgnss3ZhzjYb9" target="_blank">View location</a>
</li>
</ul>
<h2 id="content">Learning objectives</h2>
<p>
A student who has successfully completed the summer school will be able to:
</p>
<ul style="margin-top: -1em;">
<li> <strong>Explain</strong> the fundamentals of semiconductor devices.</li>
<li> <strong>Explain</strong> all steps in the chip design process.</li>
<li> <strong>Apply</strong> principles of agile hardware design to <strong>describe</strong> and <strong>implement</strong> digital systems.</li>
<li> <strong>Explain</strong> and <strong>analyze</strong> analog and mixed-signal design challenges.</li>
<li> <strong>Explain</strong> and use simple verification tools to ensure proper hardware functionality.</li>
<li> <strong>Describe</strong> the importance of sustainability for hardware designs.</li>
<li> <strong>Compare</strong> asynchronous circuits with synchronous designs to <strong>evaluate</strong> their advantages and limitations.</li>
<li> <strong>Illustrate</strong> the role and functionality of on-chip interconnects in modern chip architectures. </li>
</ul>
<hr>
<h1 id="pre-registration">Student pre-registration</h1>
<p>
Participation in the Edu4Chip Summer School is <strong>free of charge</strong> for <strong>students</strong>. However, due to limited capacity, we require all interested student participants to pre-register. This process helps us ensure a diverse and balanced group of students from different institutions and backgrounds.
</p>
<p>
To pre-register, please complete the <strong>Pre-registration</strong> by <strong>March 31th, 2025</strong>. After reviewing all applications, selected participants will receive a confirmation of admission via email and you will be prompted to the registration portal.
</p>
<ul class="actions" style="padding-left: 0px;">
<li><a href="https://www.conferencemanager.dk/pre-registrationedu4chipsummerschool2025onchipdesign" class="button big" target="_blank">Pre-register Now!</a></li></br>
</ul>
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Note: link is currently inactive - send your pre-registration at <a href="mailto:lpez@dtu.dk">lpez@dtu.dk</a>.
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<p>
<strong>Important Information:</strong>
</p>
<ul style="margin-top: -1em;">
<li><strong>Pre-Registration deadline:</strong> March 31th, 2025</li>
<li><strong>Student participation fee:</strong> Free of charge</li>
<li><strong>What is included:</strong> All lectures, keynotes, program materials, snacks, and lunches.</li>
<li><strong>Not included:</strong> Travel, accommodation, private expenses, and social activities (optional), which must be covered by participants.</li>
</ul>
<p>
For those in need of financial support for the expenses that are not included, please refer to the <a href="#financial-support">Financial support</a> section for information on available funding options. Please note that the deadline for applying for financial support depends on the institution you are from and might be earlier than the pre-registration deadline (see the <a href="#financial-support">Financial support</a> section).
</p>
<hr>
<h1 id="financial-support">Student financial support</h1>
<p>
To support student participation in the Edu4Chip Summer School from countries outside Denmark, two financial support options are availble to help cover travel and accommodation costs.
</p>
<h3>Support via Erasmus+ Blended Intensive Program (BIP)</h3>
<p>
The support via <strong>Erasmus+ Blended Intensive Program (BIP)</strong> is available to students from any <strong>DTU Erasmus+ partner institutions</strong>. This support helps cover travel, accommodation, and other expenses for eligible participants.
</p>
<p>
<strong>Eligibility:</strong> Students enrolled at DTU Erasmus+ partner institutions. In the context of Edu4Chip, these are KTH Royal Institute of Technology, Technical University of Munich (TUM), and Tampere University (Finland). However, students from other institutions that are <strong>Erasmus+ partners</strong> of DTU might be eligible for this support. Please contact your institution's international/Erasmus office for application details and procedures.
</p>
<h3>Support via Edu4Chip</h3>
<p>
The <strong>Edu4Chip project</strong> can provides financial support for students from <strong>Edu4Chip partner institutions</strong> to cover travel, accommodation, and other expenses related to the participation in the summer school.
</p>
<p>
<strong>Eligibility:</strong> Students from all Edu4Chip partner universities .<br>
</p>
<h3>More information and applications</h3>
<p>
If you are from one of the Edu4Chip partners, see the contact person in your institution below.
If you are from another university, you might still be eligible for support via <strong>Erasmus+ Blended Intensive Program (BIP)</strong>, if your institution is an <strong>Erasmus+ partner</strong> of DTU. Please contact your institution's international/Erasmus office for application details and procedures.
</p>
<p>
<h4>For students from the Technical University of Munich (TUM):</h4>
<table>
<tbody>
<tr>
<td style="max-width:100%; white-space:nowrap; width:75px;">
<img src="images/michael_pehl.jpg" alt="" style="vertical-align:top; width:75px;"/>
</td>
<td>
<strong>Contact person: </strong>PD Dr.-Ing. habil. Michael Pehl</br>
<strong>Mail: </strong><a href="mailto:m.pehl@tum.de">m.pehl@tum.de</a></br>
<strong>Phone:</strong> +49 (89) 289 - 28252</br>
<strong>Homepage: </strong><a href="https://www.ce.cit.tum.de/eisec/mitarbeiter/michael-pehl/">Link to homepage</a></br>
</td>
</tr>
</tbody>
</table>
</p>
<p>
<h4>For students from KTH Royal Institute of Technology:</h4>
<table>
<tbody>
<tr>
<td style="max-width:100%; white-space:nowrap; width:75px;">
<img src="images/ahmed_hemani.jpg" alt="" style="vertical-align:top; width:75px;"/>
</td>
<td>
<strong>Contact person: </strong>Prof. Ahmed Hemani</br>
<strong>Mail: </strong><a href="mailto:hemani@kth.se">hemani@kth.se</a></br>
<strong>Phone:</strong> +46 8 790 44 69</br>
<strong>Homepage: </strong><a href="https://www.kth.se/profile/hemani/">Link to homepage</a></br>
</td>
</tr>
</tbody>
</table>
</p>
<p>
<h4>For students from Tampere University (TAU):</h4>
<table>
<tbody>
<tr>
<td style="max-width:100%; white-space:nowrap; width:75px;">
<img src="images/timo_hamalainen.jpg" alt="" style="vertical-align:top; width:75px;"/>
</td>
<td>
<strong>Contact person: </strong>Prof. Timo Hämäläinen</br>
<strong>Mail: </strong><a href="mailto:timo.hamalainen@tuni.fi">timo.hamalainen@tuni.fi</a></br>
<strong>Phone:</strong> +35 8408490777</br>
<strong>Homepage: </strong><a href="https://www.tuni.fi/en/people/timo-hamalainen">Link to homepage</a></br>
</td>
</tr>
</tbody>
</table>
</p>
<p>
<h4>For students from Institut Mines-Télécom (IMT):</h4>
<table>
<tbody>
<tr>
<td style="max-width:100%; white-space:nowrap; width:75px;">
<img src="images/jean-max_dutertre.jpg" alt="" style="vertical-align:top; width:75px;"/>
</td>
<td>
<strong>Contact person: </strong>Prof. Jean-Max Dutertre</br>
<strong>Mail: </strong><a href="mailto:dutertre@emse.fr ">dutertre@emse.fr </a></br>
<strong>Phone:</strong> +33 (0)4 42 61 67 36</br>
<strong>Homepage: </strong><a href="https://www.emse.fr/~dutertre/index.html">Link to homepage</a></br>
</td>
</tr>
</tbody>
</table>
</p>
<p>
<h4>For students from the Technical University of Denmark (DTU):</h4>
<table>
<tbody>
<tr>
<td style="max-width:100%; white-space:nowrap; width:75px;">
<img src="images/luca_pezzarossa.jpg" alt="" style="vertical-align:top; width:75px;"/>
</td>
<td>
<strong>Contact person: </strong>Assoc. Prof. Luca Pezzarossa</br>
<strong>Mail: </strong><a href="mailto:lpez@dtu.dk">lpez@dtu.dk</a></br>
<!--strong>Phone:</strong> ???</br-->
<strong>Homepage: </strong><a href="https://orbit.dtu.dk/en/persons/luca-pezzarossa">Link to homepage</a></br>
</td>
</tr>
</tbody>
</table>
</p>
<p>
We encourage all interested students to apply early to secure funding support.
</p>
<hr>
<h1 id="other_information">Other information</h1>
<h2 id="content">DTU's 3-week special course</h2>
<p>
For <strong>DTU students only</strong>, we plan to integrate the summer school into a <strong>DTU 3-week special course</strong> worth <strong>5 ECTS</strong>, which includes an additional project week to further develop and apply the concepts learned. The course reposnible will be <strong>Luca Pezzarossa</strong> and the course will be structured as follows.
</p>