main.c

 /**
 ******************************************************************************
 * @file    main.c
 * @author  GPM Application Team
 *
 ******************************************************************************
 * @attention
 *
 * Copyright (c) 2023 STMicroelectronics.
 * All rights reserved.
 *
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 *
 ******************************************************************************
 */
#include <string.h>
#include <unistd.h>
#include <stdio.h>

#include "stm32n6570_discovery_xspi.h"
#include "stm32n6570_discovery.h"

#include "stai.h"
#include "stai_network.h"

#include "app_fuseprogramming.h"
#include "main.h"

UART_HandleTypeDef huart1;

// timer
TIM_HandleTypeDef htim6;
static uint32_t tim6_prescaler = 20000;   // sampling time 50us

// NN related variables
stai_ptr nn_in;
STAI_NETWORK_CONTEXT_DECLARE(network_context, STAI_NETWORK_CONTEXT_SIZE)

static void SystemClock_Config(void);
static void CONSOLE_Config(void);
static void Security_Config(void);
static void IAC_Config(void);
static void set_clk_sleep_mode(void);
static void Timer_Config(void);
static void Hardware_init(void);
static void Error_Handler(void);


static void NPURam_enable(void);
static void NPUCache_config(void);
static void Run_Inference(stai_network *network_instance);
static void NeuralNetwork_init(uint32_t *nn_in_length, stai_ptr *nn_out, stai_size *number_output, int32_t nn_out_len[]);



/**
  * @brief  Main program
  * @param  None
  * @retval None
  */
int main(void)
{
  Hardware_init();

  printf("Hardware initialized\n");
  printf("Hello there, I am alive!\n");

  /*** NN Init ****************************************************************/
  printf("Initializing Neural Network\n");
  uint32_t nn_in_len = 0;
  stai_size number_output = 0;
  stai_ptr nn_out[STAI_NETWORK_OUT_NUM] = {0};
  int32_t nn_out_len[STAI_NETWORK_OUT_NUM] = {0};
  printf("Initialized Neural Network\n");

  NeuralNetwork_init(&nn_in_len, nn_out, &number_output, nn_out_len);
  uint32_t i = 0;
  float trial_inputs[] = {0.0, 0.0,
                         0.0, -1.0,
                         -1.0, 0.0,
                         -1.0, -1.0,
                         0.5, 0.5,
                         0.5, -0.5,
                         -0.5, 0.5,
                         -0.5, -0.5}; 
  float sampling_time_us = (float) (1 / 400.0f * tim6_prescaler);  // in us
  
  while (1) {
    float *input = (float *)nn_in;
    for (int j = 0; j < 16; j+=2) {
      input[0] = trial_inputs[j];
      input[1] = trial_inputs[j+1];
      SCB_CleanInvalidateDCache_by_Addr(nn_in, nn_in_len);  // ensure data is flushed to memory before starting inference
      uint16_t start_time = __HAL_TIM_GET_COUNTER(&htim6);
      Run_Inference(network_context);
      uint16_t end_time = __HAL_TIM_GET_COUNTER(&htim6);
      float time_taken = ((uint16_t) (end_time - start_time)) * sampling_time_us;  // convert to us
      printf("Inference time: %7.0f us, ", time_taken);
      float real_result = trial_inputs[j] + trial_inputs[j+1] * 2;
      printf("%7.4f, %7.4f -> %7.4f, error= %7.4f \n",
        trial_inputs[j], 
        trial_inputs[j+1], 
        *((float *)nn_out[0]),
        real_result - *((float *)nn_out[0])
      );
      HAL_Delay(1000);
    }
    i++;
  }
}

static void Run_Inference(stai_network *network_instance) {
  stai_return_code ret;

  do {
    ret = stai_network_run(network_instance, STAI_MODE_ASYNC);
    if (ret == STAI_RUNNING_WFE)
      LL_ATON_OSAL_WFE();
  } while (ret == STAI_RUNNING_WFE || ret == STAI_RUNNING_NO_WFE);

  ret = stai_ext_network_new_inference(network_instance);
  assert(ret == STAI_SUCCESS);
}

static void NeuralNetwork_init(uint32_t *nn_in_length, stai_ptr *nn_out, stai_size *number_output, int32_t nn_out_len[])
{
  stai_network_info info;
  int ret;

  /* initialize runtime */
  ret = stai_runtime_init();
  assert(ret == STAI_SUCCESS);
  /* init model instance */
  ret = stai_network_init(network_context);
  assert(ret == STAI_SUCCESS);

  ret = stai_network_get_info(network_context, &info);
  assert(ret == STAI_SUCCESS);
  assert(info.n_inputs == 1);
  *number_output = STAI_NETWORK_OUT_NUM;

  /* Get the input buffer size & address */
  *nn_in_length = info.inputs[0].size_bytes;
  ret = stai_network_get_inputs(network_context, &nn_in, (stai_size *)&info.n_inputs);
  assert(ret == STAI_SUCCESS);

  /* Get the output buffers size & address */
  ret = stai_network_get_outputs(network_context, nn_out, number_output);
  assert(ret == STAI_SUCCESS);
  for (int i = 0; i < *number_output; i++)
  {
    nn_out_len[i] = info.outputs[i].size_bytes;
  }
}


static void Hardware_init(void)
{
  /* Power on ICACHE */
  MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_ICACTIVE_Msk;

  // /* Set back system and CPU clock source to HSI */
  // __HAL_RCC_CPUCLK_CONFIG(RCC_CPUCLKSOURCE_HSI);
  // __HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_HSI);

  HAL_Init();

  SCB_EnableICache();

#if defined(USE_DCACHE)
  /* Power on DCACHE */
  MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_DCACTIVE_Msk;
  SCB_EnableDCache();
#endif

  SystemClock_Config();

  CONSOLE_Config();

  Timer_Config();

  NPURam_enable();

  Fuse_Programming();

  NPUCache_config();

  /*** External RAM and NOR Flash *********************************************/
  BSP_XSPI_RAM_Init(0);
  BSP_XSPI_RAM_EnableMemoryMappedMode(0);

  /* Set all required IPs as secure privileged */
  Security_Config();

  IAC_Config();
  set_clk_sleep_mode();

}

static void NPURam_enable(void)
{
  __HAL_RCC_NPU_CLK_ENABLE();
  __HAL_RCC_NPU_FORCE_RESET();
  __HAL_RCC_NPU_RELEASE_RESET();

  /* Enable NPU RAMs (4x448KB) */
  __HAL_RCC_AXISRAM3_MEM_CLK_ENABLE();
  __HAL_RCC_AXISRAM4_MEM_CLK_ENABLE();
  __HAL_RCC_AXISRAM5_MEM_CLK_ENABLE();
  __HAL_RCC_AXISRAM6_MEM_CLK_ENABLE();
  __HAL_RCC_RAMCFG_CLK_ENABLE();
  RAMCFG_HandleTypeDef hramcfg = {0};
  hramcfg.Instance =  RAMCFG_SRAM3_AXI;
  HAL_RAMCFG_EnableAXISRAM(&hramcfg);
  hramcfg.Instance =  RAMCFG_SRAM4_AXI;
  HAL_RAMCFG_EnableAXISRAM(&hramcfg);
  hramcfg.Instance =  RAMCFG_SRAM5_AXI;
  HAL_RAMCFG_EnableAXISRAM(&hramcfg);
  hramcfg.Instance =  RAMCFG_SRAM6_AXI;
  HAL_RAMCFG_EnableAXISRAM(&hramcfg);
}

static void set_clk_sleep_mode(void)
{
  /*** Enable sleep mode support during NPU inference *************************/
  /* Configure peripheral clocks to remain active during sleep mode */
  /* Keep all IP's enabled during WFE so they can wake up CPU. Fine tune
   * this if you want to save maximum power
   */
  __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE();    /* For display frame buffer */
  __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE();    /* For NN weights */
  __HAL_RCC_NPU_CLK_SLEEP_ENABLE();      /* For NN inference */
  __HAL_RCC_CACHEAXI_CLK_SLEEP_ENABLE(); /* For NN inference */
  __HAL_RCC_LTDC_CLK_SLEEP_ENABLE();     /* For display */
  __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE();    /* For display */
  __HAL_RCC_DCMIPP_CLK_SLEEP_ENABLE();   /* For camera configuration retention */
  __HAL_RCC_CSI_CLK_SLEEP_ENABLE();      /* For camera configuration retention */

  __HAL_RCC_FLEXRAM_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM1_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM2_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM3_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM4_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM5_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM6_MEM_CLK_SLEEP_ENABLE(); 

}


static void NPUCache_config(void)
{
  npu_cache_enable();
}

static void Security_Config(void)
{
  __HAL_RCC_RIFSC_CLK_ENABLE();
  RIMC_MasterConfig_t RIMC_master = {0};
  RIMC_master.MasterCID = RIF_CID_1;
  RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_NPU, &RIMC_master);
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_DMA2D, &RIMC_master);
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_DCMIPP, &RIMC_master);
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_LTDC1 , &RIMC_master);
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_LTDC2 , &RIMC_master);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_NPU , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_DMA2D , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_CSI    , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_DCMIPP , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_LTDC   , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_LTDCL1 , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_LTDCL2 , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
}

static void IAC_Config(void)
{
/* Configure IAC to trap illegal access events */
  __HAL_RCC_IAC_CLK_ENABLE();
  __HAL_RCC_IAC_FORCE_RESET();
  __HAL_RCC_IAC_RELEASE_RESET();
}

void IAC_IRQHandler(void)
{
  while (1)
  {
  }
}

/**
  * @brief  DCMIPP Clock Config for DCMIPP.
  * @param  hdcmipp  DCMIPP Handle
  *         Being __weak it can be overwritten by the application
  * @retval HAL_status
  */
HAL_StatusTypeDef MX_DCMIPP_ClockConfig(DCMIPP_HandleTypeDef *hdcmipp)
{
  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};
  HAL_StatusTypeDef ret = HAL_OK;

  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_DCMIPP;
  RCC_PeriphCLKInitStruct.DcmippClockSelection = RCC_DCMIPPCLKSOURCE_IC17;
  RCC_PeriphCLKInitStruct.ICSelection[RCC_IC17].ClockSelection = RCC_ICCLKSOURCE_PLL2;
  RCC_PeriphCLKInitStruct.ICSelection[RCC_IC17].ClockDivider = 3;
  ret = HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
  if (ret)
  {
    return ret;
  }

  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CSI;
  RCC_PeriphCLKInitStruct.ICSelection[RCC_IC18].ClockSelection = RCC_ICCLKSOURCE_PLL1;
  RCC_PeriphCLKInitStruct.ICSelection[RCC_IC18].ClockDivider = 40;
  ret = HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
  if (ret)
  {
    return ret;
  }

  return ret;
}

static void SystemClock_Config(void)
{
  // RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  // RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  // RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};

  // /* Ensure VDDCORE=0.9V before increasing the system frequency */
  // BSP_SMPS_Init(SMPS_VOLTAGE_OVERDRIVE);

  // RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_NONE;

  // /* PLL1 = 64 x 25 / 2 = 800MHz */
  // RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
  // RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSI;
  // RCC_OscInitStruct.PLL1.PLLM = 2;
  // RCC_OscInitStruct.PLL1.PLLN = 25;
  // RCC_OscInitStruct.PLL1.PLLFractional = 0;
  // RCC_OscInitStruct.PLL1.PLLP1 = 1;
  // RCC_OscInitStruct.PLL1.PLLP2 = 1;

  // /* PLL2 = 64 x 125 / 8 = 1000MHz */
  // RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
  // RCC_OscInitStruct.PLL2.PLLSource = RCC_PLLSOURCE_HSI;
  // RCC_OscInitStruct.PLL2.PLLM = 8;
  // RCC_OscInitStruct.PLL2.PLLFractional = 0;
  // RCC_OscInitStruct.PLL2.PLLN = 125;
  // RCC_OscInitStruct.PLL2.PLLP1 = 1;
  // RCC_OscInitStruct.PLL2.PLLP2 = 1;

  // /* PLL3 = (64 x 225 / 8) / (1 * 2) = 900MHz */
  // RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
  // RCC_OscInitStruct.PLL3.PLLSource = RCC_PLLSOURCE_HSI;
  // RCC_OscInitStruct.PLL3.PLLM = 8;
  // RCC_OscInitStruct.PLL3.PLLN = 225;
  // RCC_OscInitStruct.PLL3.PLLFractional = 0;
  // RCC_OscInitStruct.PLL3.PLLP1 = 1;
  // RCC_OscInitStruct.PLL3.PLLP2 = 2;

  // /* PLL4 = (64 x 225 / 8) / (6 * 6) = 50 MHz */
  // RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
  // RCC_OscInitStruct.PLL4.PLLSource = RCC_PLLSOURCE_HSI;
  // RCC_OscInitStruct.PLL4.PLLM = 8;
  // RCC_OscInitStruct.PLL4.PLLFractional = 0;
  // RCC_OscInitStruct.PLL4.PLLN = 225;
  // RCC_OscInitStruct.PLL4.PLLP1 = 6;
  // RCC_OscInitStruct.PLL4.PLLP2 = 6;

  // if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  // {
  //   while(1);
  // }

  // RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK |
  //                                RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 |
  //                                RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 |
  //                                RCC_CLOCKTYPE_PCLK5);

  // /* CPU CLock (sysa_ck) = ic1_ck = PLL1 output/ic1_divider = 800 MHz */
  // RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1;
  // RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11;
  // RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
  // RCC_ClkInitStruct.IC1Selection.ClockDivider = 1;

  // /* AXI Clock (sysb_ck) = ic2_ck = PLL1 output/ic2_divider = 400 MHz */
  // RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
  // RCC_ClkInitStruct.IC2Selection.ClockDivider = 2;

  // /* NPU Clock (sysc_ck) = ic6_ck = PLL2 output/ic6_divider = 1000 MHz */
  // RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL2;
  // RCC_ClkInitStruct.IC6Selection.ClockDivider = 1;

  // /* AXISRAM3/4/5/6 Clock (sysd_ck) = ic11_ck = PLL3 output/ic11_divider = 900 MHz */
  // RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL3;
  // RCC_ClkInitStruct.IC11Selection.ClockDivider = 1;

  // /* HCLK = sysb_ck / HCLK divider = 200 MHz */
  // RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;

  // /* PCLKx = HCLK / PCLKx divider = 200 MHz */
  // RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
  // RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
  // RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
  // RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1;

  // if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK)
  // {
  //   while(1);
  // }

  // // init peripherals clocks
  // RCC_PeriphCLKInitStruct.PeriphClockSelection = 0;

  // /* XSPI1 kernel clock (ck_ker_xspi1) = HCLK = 200MHz */
  // RCC_PeriphCLKInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_XSPI1;
  // RCC_PeriphCLKInitStruct.Xspi1ClockSelection = RCC_XSPI1CLKSOURCE_HCLK;

  // /* XSPI2 kernel clock (ck_ker_xspi1) = HCLK =  200MHz */
  // RCC_PeriphCLKInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_XSPI2;
  // RCC_PeriphCLKInitStruct.Xspi2ClockSelection = RCC_XSPI2CLKSOURCE_HCLK;

  // // timer clock source set to same as sysb_ck
  // RCC_PeriphCLKInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_TIM;
  // RCC_PeriphCLKInitStruct.TIMPresSelection = RCC_TIMPRES_DIV1;


  // if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK)
  // {
  //   while (1);
  // }
}

/**
  * @brief Timer initialization funciton
  * @param None
  * @retval None
  */
static void Timer_Config(void)
{
  // Note: input clock to timer is 400MHz 
  TIM_MasterConfigTypeDef sMasterConfig = {0};
  // configure timer 6 as a stopwatch to measure inference time. 
  // It will run continuously and we will read the counter value before and after inference to get the time taken.
  // enable clock
  __HAL_RCC_TIM6_CLK_ENABLE();
  htim6.Instance = TIM6;
  htim6.Init.Prescaler = tim6_prescaler - 1;
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
  htim6.Init.Period = 65535;
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
  {
    Error_Handler();
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
  {
    Error_Handler();
  }
  HAL_TIM_Base_Start(&htim6);

}

/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
static void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
  {
  }
  /* USER CODE END Error_Handler_Debug */
}

static void CONSOLE_Config()
{
  GPIO_InitTypeDef gpio_init;

  __HAL_RCC_USART1_CLK_ENABLE();
  __HAL_RCC_GPIOE_CLK_ENABLE();

 /* DISCO & NUCLEO USART1 (PE5/PE6) */
  gpio_init.Mode      = GPIO_MODE_AF_PP;
  gpio_init.Pull      = GPIO_PULLUP;
  gpio_init.Speed     = GPIO_SPEED_FREQ_HIGH;
  gpio_init.Pin       = GPIO_PIN_5 | GPIO_PIN_6;
  gpio_init.Alternate = GPIO_AF7_USART1;
  HAL_GPIO_Init(GPIOE, &gpio_init);

  huart1.Instance          = USART1;
  huart1.Init.BaudRate     = 115200;
  huart1.Init.Mode         = UART_MODE_TX_RX;
  huart1.Init.Parity       = UART_PARITY_NONE;
  huart1.Init.WordLength   = UART_WORDLENGTH_8B;
  huart1.Init.StopBits     = UART_STOPBITS_1;
  huart1.Init.HwFlowCtl    = UART_HWCONTROL_NONE;
  huart1.Init.OverSampling = UART_OVERSAMPLING_8;
  if (HAL_UART_Init(&huart1) != HAL_OK)
  {
    while (1);
  }
}

int _write(int file, char *ptr, int len)
{
  HAL_StatusTypeDef status;
  status = HAL_UART_Transmit(&huart1, (uint8_t*)ptr, len, ~0);

  return (status == HAL_OK ? len : 0);
}

void npu_cache_enable_clocks_and_reset(void)
{
  __HAL_RCC_CACHEAXIRAM_MEM_CLK_ENABLE();
  __HAL_RCC_CACHEAXI_CLK_ENABLE();
  __HAL_RCC_CACHEAXI_FORCE_RESET();
  __HAL_RCC_CACHEAXI_RELEASE_RESET();
}

void npu_cache_disable_clocks_and_reset(void)
{
  __HAL_RCC_CACHEAXIRAM_MEM_CLK_DISABLE();
  __HAL_RCC_CACHEAXI_CLK_DISABLE();
  __HAL_RCC_CACHEAXI_FORCE_RESET();
}

#ifdef  USE_FULL_ASSERT

/**
  * @brief  Reports the name of the source file and the source line number
  *         where the assert_param error has occurred.
  * @param  file: pointer to the source file name
  * @param  line: assert_param error line source number
  * @retval None
  */
void assert_failed(uint8_t* file, uint32_t line)
{
  UNUSED(file);
  UNUSED(line);
  __BKPT(0);
  while (1)
  {
  }
}

#endif